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Toward Multi-FPGA Acceleration of the Neural Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.media.2017.07.005openalex-snapshot
A survey on deep learning in medical image analysis
inferredcites →https://doi.org/10.1109/cvpr.2016.435openalex-snapshot
Fast Algorithms for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/fpt.2017.8280160openalex-snapshot
PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks
inferredcites →https://doi.org/10.1109/iccv.1995openalex-snapshot
Proceedings of IEEE International Conference on Computer Vision
inferredcites →https://doi.org/10.1109/iccv.2015.510openalex-snapshot
Learning Spatiotemporal Features with 3D Convolutional Networks
inferredcites →https://doi.org/10.1109/iros.2015.7353481openalex-snapshot
VoxNet: A 3D Convolutional Neural Network for real-time object recognition
inferredcites →https://doi.org/10.1109/isca.2018.00012openalex-snapshot
A Configurable Cloud-Scale DNN Processor for Real-Time AI
inferredcites →https://doi.org/10.1109/iscas.2017.8050344openalex-snapshot
End-to-end scalable FPGA accelerator for deep residual networks
inferredcites →https://doi.org/10.1109/msp.2017.2743240openalex-snapshot
Deep Reinforcement Learning: A Brief Survey
inferredcites →https://doi.org/10.1109/tcad.2017.2785257openalex-snapshot
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/tpami.2012.59openalex-snapshot
3D Convolutional Neural Networks for Human Action Recognition
inferredcites →https://doi.org/10.1109/tvlsi.2018.2815603openalex-snapshot
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
inferredcites →https://doi.org/10.1137/0209021openalex-snapshot
On Multiplication of Polynomials Modulo a Polynomial
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2847263.2847276openalex-snapshot
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/2934583.2934644openalex-snapshot
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3174243.3174257openalex-snapshot
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA
inferredcites →https://doi.org/10.1145/3242898openalex-snapshot
You Cannot Improve What You Do not Measure
inferredcites →https://doi.org/10.1145/3358181openalex-snapshot
End-to-End Timing Analysis of Sporadic Cause-Effect Chains in Distributed Systems
inferredcites →https://doi.org/10.1145/3358192openalex-snapshot
Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference
inferredcites →https://doi.org/10.3390/electronics8010065openalex-snapshot
A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Design of 3D Point Cloud Real-Time Cloud Matching Algorithm Based on Multi-scale Feature Extraction
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FPGA-Based Implementation of an RBF-PID Neural Network for Adaptive Parameter Tuning
inferred← citeshttps://doi.org/10.1007/978-981-96-0096-0_31openalex-snapshot
Design of FPGA Hardware Accelerator Based on Convolutional Neural Network
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FPGA-Based Adaptive Modeling Method for Modular Robots
inferred← citeshttps://doi.org/10.1016/j.jpdc.2022.04.025openalex-snapshot
Towards a component-based acceleration of convolutional neural networks on FPGAs
inferred← citeshttps://doi.org/10.1038/s41598-024-68998-0openalex-snapshot
Optimization of UWB indoor positioning based on hardware accelerated Fuzzy ISODATA
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Microwave-Modulated Spintronic Stochastic Neuron Based on a Magnetic Tunnel Junction
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DF-TEE: Trusted Execution Environment for Disaggregated Multi-FPGA Cloud Systems
inferred← citeshttps://doi.org/10.1109/ceeml65709.2024.00021openalex-snapshot
Design and Implementation of Lightweight Neural Network Inference Accelerator Based on FPGA
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00043openalex-snapshot
Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00079openalex-snapshot
Accelerating Hybrid Quantized Neural Networks on Multi-tenant Cloud FPGA
inferred← citeshttps://doi.org/10.1109/icpeca60615.2024.10471036openalex-snapshot
Low-Power Design of Advanced Image Processing Algorithms under FPGA in Real-Time Applications
inferred← citeshttps://doi.org/10.1109/icsmd57530.2022.10058241openalex-snapshot
Optimized Acceleration of Single Shot Detection for Edge Computing Based-on FPGA
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Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms
inferred← citeshttps://doi.org/10.1109/ispdc55340.2022.00014openalex-snapshot
Coarse-Grained Floorplanning for streaming CNN applications on Multi-Die FPGAs
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014348openalex-snapshot
LUTAccel: Look-up-Table Based Vector Systolic Accelerator on FPGAs
inferred← citeshttps://doi.org/10.1109/isset62871.2024.10779767openalex-snapshot
Research on Hardware Acceleration Technique for Weight-Based Fixed Pulsed Arrays
inferred← citeshttps://doi.org/10.1109/isvlsi65124.2025.11130267openalex-snapshot
HEDGY: Heterogeneous Design Management for Multi-Tenant Multi-FPGA Edge Systems
inferred← citeshttps://doi.org/10.1109/nnice68970.2026.11465526openalex-snapshot
Pipelined Serial Multiplier Achieve Higher Speed and Energy Efficiency in FPGA Based Convolutional Neural Network
inferred← citeshttps://doi.org/10.1109/sbcci62366.2024.10704009openalex-snapshot
ADARE: Adaptive Resource Provisioning in Multi-FPGA Edge Environments
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Gemini: a Real-time Video Analytics System with Dual Computing Resource Control
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Scalable Multi-FPGA HPC Architecture for Associative Memory System
inferred← citeshttps://doi.org/10.1109/tc.2023.3301136openalex-snapshot
An Edge-Side Real-Time Video Analytics System With Dual Computing Resource Control
inferred← citeshttps://doi.org/10.1109/tmc.2025.3550519openalex-snapshot
LVMScissor: Split and Schedule Large Vision Model Inference on Mobile Edges via Salp Swarm Algorithm
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3716149openalex-snapshot
HEADS: Accuracy--Makespan Co-Optimization for Multitenant Multi-FPGA Edge Systems
inferred← citeshttps://doi.org/10.1109/uemcon54665.2022.9965651openalex-snapshot
FPGA Acceleration of a Real-time Neural Network Controller for Solar Inverter
inferred← citeshttps://doi.org/10.1142/s0218126623500755openalex-snapshot
A Resource Efficient CNN Accelerator for Sensor Signal Processing Based on FPGA
inferred← citeshttps://doi.org/10.1145/3506713openalex-snapshot
The Future of FPGA Acceleration in Datacenters and the Cloud
inferred← citeshttps://doi.org/10.1145/3728179.3728186openalex-snapshot
Accelerating Deep Learning Inference with a Parallel FPGA System
inferred← citeshttps://doi.org/10.2139/ssrn.5449826openalex-snapshot
A Scalable Framework for Accelerating Neural Networks in Multi-Die Cloud FPGAs
inferred← citeshttps://doi.org/10.23919/date56975.2023.10136962openalex-snapshot
M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137117openalex-snapshot
Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms
inferred← citeshttps://doi.org/10.3390/electronics13122280openalex-snapshot
An FPGA-Accelerated CNN with Parallelized Sum Pooling for Onboard Realtime Routing in Dynamic Low-Orbit Satellite Networks
inferred← citeshttps://doi.org/10.3390/electronics13173504openalex-snapshot
A Scalable Multi-FPGA Platform for Hybrid Intelligent Optimization Algorithms
inferred← citeshttps://doi.org/10.3390/electronics13214189openalex-snapshot
Beam Orbital Parameter Prediction Based on the Deployment of Cascaded Neural Networks at Edge Intelligence Acceleration Nodes
inferred← citeshttps://doi.org/10.3390/s22176618openalex-snapshot
A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs and Its FPGA Implementation
inferred← citeshttps://doi.org/10.3390/s23020824openalex-snapshot
A Hardware-Friendly High-Precision CNN Pruning Method and Its FPGA Implementation
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