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Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/asap.2019.00-31openalex-snapshot
Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays
inferredcites →https://doi.org/10.1109/cvpr.2009.5206848openalex-snapshot
ImageNet: A large-scale hierarchical image database
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/cvpr.2017.195openalex-snapshot
Xception: Deep Learning with Depthwise Separable Convolutions
inferredcites →https://doi.org/10.1109/hcs49909.2020.9220735openalex-snapshot
Google's Training Chips Revealed: TPUv2 and TPUv3
inferredcites →https://doi.org/10.1109/hpca.2017.29openalex-snapshot
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/hpca47549.2020.00015openalex-snapshot
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training
inferredcites →https://doi.org/10.1109/iscas45731.2020.9180403openalex-snapshot
A Systolic Dataflow Based Accelerator for CNNs
inferredcites →https://doi.org/10.1109/ispass48437.2020.00016openalex-snapshot
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
inferredcites →https://doi.org/10.1109/isvlsi49217.2020.00088openalex-snapshot
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator
inferredcites →https://doi.org/10.1109/jetcas.2019.2910232openalex-snapshot
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/lca.2019.2924007openalex-snapshot
SMT-SA: Simultaneous Multithreading in Systolic Arrays
inferredcites →https://doi.org/10.1109/lca.2020.2979965openalex-snapshot
Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference
inferredcites →https://doi.org/10.1109/mwscas.2012.6292202openalex-snapshot
NeuFlow: Dataflow vision processing system-on-a-chip
inferredcites →https://doi.org/10.1142/s1793351x16500045openalex-snapshot
Deep Learning
inferredcites →https://doi.org/10.1145/2541940.2541967openalex-snapshot
DianNao
inferredcites →https://doi.org/10.1145/2749469.2750389openalex-snapshot
ShiDianNao
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3065386openalex-snapshot
ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.1145/3173162.3173176openalex-snapshot
MAERI
inferredcites →https://doi.org/10.1145/3297858.3304028openalex-snapshot
Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations
inferredcites →https://doi.org/10.1145/3307650.3322255openalex-snapshot
Laconic deep learning inference acceleration
inferredcites →https://doi.org/10.1145/3352460.3358252openalex-snapshot
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow
inferredcites →https://doi.org/10.1145/3352460.3358302openalex-snapshot
Simba
inferredcites →https://doi.org/10.1162/neco.1989.1.4.541openalex-snapshot
Backpropagation Applied to Handwritten Zip Code Recognition
inferredcites →https://doi.org/10.48550/arxiv.1905.11946openalex-snapshot
EfficientNet: Rethinking Model Scaling for Convolutional Neural Networks
inferredcites →https://doi.org/10.57702/zp44cu3gopenalex-snapshot
Learning Multiple Layers of Features from Tiny Images

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Optimizing the Parallelism of Communication and Computation in Distributed Training Platform
inferred← citeshttps://doi.org/10.1016/j.mejo.2025.106831openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2023.104938openalex-snapshot
Exploiting data encoding and reordering for low-power streaming in systolic arrays
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103604openalex-snapshot
SpikeFlow: A hardware–software co-designed systolic array for spiking neural networks
inferred← citeshttps://doi.org/10.1016/j.vlsi.2025.102383openalex-snapshot
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1
inferred← citeshttps://doi.org/10.1051/itmconf/20257402007openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/cnna60945.2023.10652619openalex-snapshot
The Case for Asymmetric Systolic Array Floorplanning
inferred← citeshttps://doi.org/10.1109/elexcom58812.2023.10370584openalex-snapshot
FPGA Implementation of Systolic Array for 2D Convolution Using Residue Number System
inferred← citeshttps://doi.org/10.1109/hpcc67675.2025.00039openalex-snapshot
X-SA: An Efficient Configurable Systolic Array Computing Architecture for GPGPU
inferred← citeshttps://doi.org/10.1109/iccc62609.2024.10941946openalex-snapshot
Hardware-Accelerated 1-Bit Quantization Using PyRTL for Efficient Neural Network Design
inferred← citeshttps://doi.org/10.1109/iccd63220.2024.00078openalex-snapshot
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Design of A Low-Latency General-Purpose CNN Hardware Accelerator Based on Pulsed Arrays on FPGAs
inferred← citeshttps://doi.org/10.1109/icosec67334.2025.11459778openalex-snapshot
Redefining Systolic Efficiency with Pipelining ML Acceleration for High-Throughput AI Inference
inferred← citeshttps://doi.org/10.1109/ictest64710.2025.11042522openalex-snapshot
Novel FPGA based Systolic Array Design for Dynamic Workflows
inferred← citeshttps://doi.org/10.1109/iist62526.2024.00107openalex-snapshot
SNN Implementation Based on Systolic Arrays
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00026openalex-snapshot
HALO: Hybrid Systolic Arrays via Logical Partitioning for Acceleration of Complex-Valued Neural Networks
inferred← citeshttps://doi.org/10.1109/ikt65497.2024.10892683openalex-snapshot
Architectural Insights: Comparing Weight Stationary and Output Stationary Systolic Arrays for Efficient Computation
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043589openalex-snapshot
CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices
inferred← citeshttps://doi.org/10.1109/isocc56007.2022.10031594openalex-snapshot
An Efficient Systolic Array with Variable Data Precision and Dimension Support
inferred← citeshttps://doi.org/10.1109/mocast57943.2023.10176467openalex-snapshot
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating
inferred← citeshttps://doi.org/10.1109/ricai68060.2025.11385279openalex-snapshot
Research on a Flexibly Partitionable Scheme for Systolic Array Architecture
inferred← citeshttps://doi.org/10.1109/socc62300.2024.10737853openalex-snapshot
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability
inferred← citeshttps://doi.org/10.1109/tcad.2022.3198036openalex-snapshot
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3483308openalex-snapshot
Eyelet: A Cross-Mesh NoC-Based Fine-Grained Sparse CNN Accelerator for Spatio-Temporal Parallel Computing Optimization
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3497724openalex-snapshot
A 3-D Multi-Precision Scalable Systolic FMA Architecture
inferred← citeshttps://doi.org/10.1109/tns.2026.3691993openalex-snapshot
Heavy-Ion Radiation Fault Analysis of URSA: A Reconfigurable Systolic Array for CNN Acceleration in SRAM-Based APSoC
inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3521394openalex-snapshot
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3693713openalex-snapshot
Fused-STA: Automated Design Space Exploration of a Fused Systolic Tensor Array for Universal Deep Learning Acceleration
inferred← citeshttps://doi.org/10.1109/vlsid64188.2025.00056openalex-snapshot
Layer-Specific Hardware Pooling Designs for CNN Accelerators
inferred← citeshttps://doi.org/10.1145/3532863openalex-snapshot
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication
inferred← citeshttps://doi.org/10.1145/3549937openalex-snapshot
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array
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A Survey of Design and Optimization for Systolic Array-based DNN Accelerators
inferred← citeshttps://doi.org/10.1145/3615338.3618130openalex-snapshot
Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework
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ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations
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SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow
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EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs
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ReSA: Reconfigurable Systolic Array for Multiple Tiny DNN Tensors
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Scratchpad Memory Management for Deep Learning Accelerators
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SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks
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HopScotch: A Holistic Approach to Data Layout-Aware Mapping on NPUs for High-Performance DNN Inference
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SpMARD: A Sparse-Sparse Matrix Multiplication Accelerator with Reconfigurable Dataflow for DNN Workloads
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Xtream: A Production-Level VM Cross-Cloud Disk Migration System with Stripe-Oriented Prefetching
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Fault-Tolerant Topology Reconfiguration Framework for NoC-Based Multiprocessor Arrays via Bipartite Matching and Reinforcement Learning
inferred← citeshttps://doi.org/10.1364/oe.604976openalex-snapshot
Optical processing units vs. GPUs and TPUs: conditions for performance and energy advantage
inferred← citeshttps://doi.org/10.1631/fitee.2400867openalex-snapshot
SAPER-AI accelerator: a systolic array-based power-efficient reconfigurable AI accelerator
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Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col
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Flexible Convolver for Convolutional Neural Networks Deployment onto Hardware-Oriented Applications
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Fast Design Space Exploration for Always-On Neural Networks
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End-to-End Implementation of a Convolutional Neural Network on a 3D-Integrated Image Sensor with Macropixel Array
inferred← citeshttps://doi.org/10.3724/sp.j.1089.2023.19451openalex-snapshot
Heterogeneous Multi-Chiplets Neural Network Accelerator
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SPOTS: An Accelerator for Sparse Convolutional Networks Leveraging Systolic General Matrix-Matrix Multiplication
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Dynamic matrix multiplications in memory with photonics and phase-change materials
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