On the public citation graph

Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array

https://doi.org/10.1145/3549937
0 signed · 89 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/j.comcom.2021.10.023openalex-snapshot
Face detection algorithm based on improved TinyYOLOv3 and attention mechanism
inferredcites →https://doi.org/10.1016/j.imavis.2020.104039openalex-snapshot
A calibration method of computer vision system based on dual attention mechanism
inferredcites →https://doi.org/10.1093/bioinformatics/btab560openalex-snapshot
Learning embedding features based on multisense-scaled attention architecture to improve the predictive performance of anticancer peptides
inferredcites →https://doi.org/10.1109/apccas.2018.8605654openalex-snapshot
A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning
inferredcites →https://doi.org/10.1109/asicon47005.2019openalex-snapshot
2019 IEEE 13th International Conference on ASIC (ASICON)
inferredcites →https://doi.org/10.1109/cvpr.2018.00813openalex-snapshot
Non-local Neural Networks
inferredcites →https://doi.org/10.1109/fccm48280.2020.00074openalex-snapshot
Accelerating Large Scale GCN Inference on FPGA
inferredcites →https://doi.org/10.1109/hpca51647.2021openalex-snapshot
2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
inferredcites →https://doi.org/10.1109/hpca51647.2021.00018openalex-snapshot
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
inferredcites →https://doi.org/10.1109/icassp39728.2021.9414313openalex-snapshot
Top-Down Attention in End-to-End Spoken Language Understanding
inferredcites →https://doi.org/10.1109/isca52012.2021openalex-snapshot
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
inferredcites →https://doi.org/10.1109/isqed51717.2021.9424344openalex-snapshot
Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning
inferredcites →https://doi.org/10.1109/lca.2020.2979965openalex-snapshot
Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference
inferredcites →https://doi.org/10.1109/lgrs.2021.3100294openalex-snapshot
A Shadow Detection Algorithm Based on Multiscale Spatial Attention Mechanism for Aerial Remote Sensing Images
inferredcites →https://doi.org/10.1109/socc49529.2020.9524802openalex-snapshot
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer
inferredcites →https://doi.org/10.1109/taslp.2021.3097939openalex-snapshot
Attending From Foresight: A Novel Attention Mechanism for Neural Machine Translation
inferredcites →https://doi.org/10.1109/tcad.2018.2824280openalex-snapshot
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/tvlsi.2019.2905242openalex-snapshot
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3289185openalex-snapshot
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
inferredcites →https://doi.org/10.1145/3370748openalex-snapshot
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design
inferredcites →https://doi.org/10.1145/3373087.3375312openalex-snapshot
GraphACT
inferredcites →https://doi.org/10.1145/3400302.3415643openalex-snapshot
FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory
inferredcites →https://doi.org/10.1145/3431920.3439292openalex-snapshot
AutoSA
inferredcites →https://doi.org/10.1145/3460776openalex-snapshot
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3466752openalex-snapshot
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
inferredcites →https://doi.org/10.1145/3476984openalex-snapshot
RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping
inferredcites →https://doi.org/10.1145/3477002openalex-snapshot
Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices
inferredcites →https://doi.org/10.1155/2021/3846078openalex-snapshot
An Attention Mechanism Oriented Hybrid CNN‐RNN Deep Learning Architecture of Container Terminal Liner Handling Conditions Prediction
inferredcites →https://doi.org/10.1162/tacl_a_00353openalex-snapshot
Efficient Content-Based Sparse Attention with Routing Transformers
inferredcites →https://doi.org/10.18653/v1/p19-1285openalex-snapshot
Transformer-XL: Attentive Language Models beyond a Fixed-Length Context
inferredcites →https://doi.org/10.18653/v1/w18-2509openalex-snapshot
The Annotated Transformer
inferredcites →https://doi.org/10.18653/v1/w18-5446openalex-snapshot
GLUE: A Multi-Task Benchmark and Analysis Platform for Natural Language Understanding
inferredcites →https://doi.org/10.2200/s01123ed1v01y202108hlt053openalex-snapshot
Pretrained Transformers for Text Ranking: BERT and Beyond
inferredcites →https://doi.org/10.23919/date48585.2020.9116469openalex-snapshot
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks
inferredcites →https://doi.org/10.23919/date51398.2021.9474215openalex-snapshot
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs
inferredcites →https://doi.org/10.4230/lipics.cosit.2022.18openalex-snapshot
AI-Assisted Pipeline for Dynamic Generation of Trustworthy Health Supplement Content at Scale
inferredcites →https://doi.org/10.4230/lipics.ecrts.2023.7openalex-snapshot
Bootstrapping a Data-Set and Model for Question-Answering in Portuguese (Short Paper)
inferredcites →https://doi.org/10.48550/arxiv.1804.07461openalex-snapshot
GLUE: A Multi-Task Benchmark and Analysis Platform for Natural Language Understanding
inferredcites →https://doi.org/10.48550/arxiv.1908.08962openalex-snapshot
Well-Read Students Learn Better: On the Importance of Pre-training Compact Models
inferredcites →https://doi.org/10.7873/date.2013openalex-snapshot
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/lpor.202501995openalex-snapshot
Photonic Systolic Array for All‐Optical Matrix–Matrix Multiplication
inferred← citeshttps://doi.org/10.1007/978-3-031-99857-7_5openalex-snapshot
CoQMoE: Co-Designed Quantization and Computation Orchestration for Mixture-of-Experts Vision Transformer on FPGA
inferred← citeshttps://doi.org/10.1007/978-3-032-16454-4_1openalex-snapshot
Transforming User Interface Designs for Mixed Reality Using a Meta-UI Tool Prototype
inferred← citeshttps://doi.org/10.1007/978-981-92-4805-6_23openalex-snapshot
Helios: Scalable Multi-accelerator FPGA Architecture for Efficient Inference of Transformer-Based Models
inferred← citeshttps://doi.org/10.1007/s11831-025-10348-yopenalex-snapshot
Optimization Strategies and Algorithms for Accelerating CNN on FPGA: A Comprehensive Review
inferred← citeshttps://doi.org/10.1016/j.future.2026.108646openalex-snapshot
HALO: A heterogeneous accelerator for low-latency and energy-efficient edge LLM inference
inferred← citeshttps://doi.org/10.1016/j.jksuci.2024.102194openalex-snapshot
High-throughput systolic array-based accelerator for hybrid transformer-CNN networks
inferred← citeshttps://doi.org/10.1016/j.micpro.2025.105223openalex-snapshot
A runtime-adaptive transformer neural network accelerator on FPGAs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102990openalex-snapshot
A survey of techniques for optimizing transformer inference
inferred← citeshttps://doi.org/10.1109/eiect68017.2025.11331702openalex-snapshot
Tightly-Coupled Transformer Accelerator Architecture Based on RISC-V
inferred← citeshttps://doi.org/10.1109/fccm62733.2025.00078openalex-snapshot
An Efficient FPGA-Based Hardware Accelerator of Fully Quantized Mamba-2
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00054openalex-snapshot
FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors
inferred← citeshttps://doi.org/10.1109/icce63647.2025.10930161openalex-snapshot
An In-Memory Computing-based Efficient Transformer Accelerator Using Stateful Matrix Multiplier for Voice Assistant Consumer Applications
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974463openalex-snapshot
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00016openalex-snapshot
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113430openalex-snapshot
Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00053openalex-snapshot
FLAA: Fused Linear Attention Accelerator for Efficient Inference and Training in Transformers: PhD Forum Paper
inferred← citeshttps://doi.org/10.1109/icicm66614.2025.11316085openalex-snapshot
Hardware Implementation and Side-Channel Security Analysis for High-Precision AI Tansformer Encoder
inferred← citeshttps://doi.org/10.1109/icosec67334.2025.11459778openalex-snapshot
Redefining Systolic Efficiency with Pipelining ML Acceleration for High-Throughput AI Inference
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00045openalex-snapshot
A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00094openalex-snapshot
BlissCam: Boosting Eye Tracking Efficiency with Learned In-Sensor Sparse Sampling
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043592openalex-snapshot
FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on FPGAs
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043956openalex-snapshot
UbiMoE: A Ubiquitous Mixture-of-Experts Vision Transformer Accelerator With Hybrid Computation Pattern on FPGA
inferred← citeshttps://doi.org/10.1109/jetcas.2025.3575272openalex-snapshot
Generative AI Through CAS Lens: An Integrated Overview of Algorithmic Optimizations, Architectural Advances, and Automated Designs
inferred← citeshttps://doi.org/10.1109/lascas67804.2026.11457118openalex-snapshot
Design and Synthesis of a Scaled Dot Product Accelerator with an AXI4-Stream Interface
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00108openalex-snapshot
Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
inferred← citeshttps://doi.org/10.1109/tbcas.2024.3436837openalex-snapshot
High-Performance Method and Architecture for Attention Computation in DNN Inference
inferred← citeshttps://doi.org/10.1109/tcad.2024.3410841openalex-snapshot
Automatic Mapping of Heterogeneous DNN Models on Adaptive Multiaccelerator Systems
inferred← citeshttps://doi.org/10.1109/tcsi.2024.3497724openalex-snapshot
A 3-D Multi-Precision Scalable Systolic FMA Architecture
inferred← citeshttps://doi.org/10.1109/tmc.2025.3567284openalex-snapshot
VerDT: A Versatile Digital Twins Framework for UAVs-Based Industrial Cyber-Physical Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3540844openalex-snapshot
An Energy-Efficient FPGA Accelerator for Swin Transformer
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3589359openalex-snapshot
DATA: A Memory-Efficient Deformable Transformer Accelerator via Neural Architecture Search
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3604705openalex-snapshot
MoE-Sched: Enabling Efficient FPGA Deployment of Mixture-of-Experts Vision Transformers via Coordinated Scheduling
inferred← citeshttps://doi.org/10.1126/science.aef8268openalex-snapshot
Hypervision: An on-chip hyperspectral microsystem for online video-rate computational imaging
inferred← citeshttps://doi.org/10.1145/3649476.3658810openalex-snapshot
Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion
inferred← citeshttps://doi.org/10.1145/3674909openalex-snapshot
ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error Detection
inferred← citeshttps://doi.org/10.1145/3676641.3716013openalex-snapshot
PICACHU: Plug-In CGRA Handling Upcoming Nonlinear Operations in LLMs
inferred← citeshttps://doi.org/10.1145/3706628.3708867openalex-snapshot
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
inferred← citeshttps://doi.org/10.1145/3714416openalex-snapshot
TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
inferred← citeshttps://doi.org/10.1145/3754598.3754656openalex-snapshot
Automated FPGA Accelerator Generation Framework for Transformers with Dataflow Optimization
inferred← citeshttps://doi.org/10.1145/3797905.3800510openalex-snapshot
DANMP: Accelerating Multi-Scale Deformable Attention Using Near-Memory-Processing Architecture
inferred← citeshttps://doi.org/10.1145/3806645.3807596openalex-snapshot
Scaling Attention Beyond GPUs for LLM Inference
inferred← citeshttps://doi.org/10.1145/3847663openalex-snapshot
Defending Side-Channel Attacks in FPGA-based Convolutional Layers and Multi-Head Attention Layers with Channel-Level Parallelization
inferred← citeshttps://doi.org/10.1360/ssi-2024-0351openalex-snapshot
FPGA Overlay processor for AI computing
inferred← citeshttps://doi.org/10.2174/0129503752352719250214061245openalex-snapshot
Enhancing GNSS Signal Integrity in Medical Logistics: A Deep Learning Solution
inferred← citeshttps://doi.org/10.3390/electronics12040822openalex-snapshot
High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays
inferred← citeshttps://doi.org/10.3390/electronics13234683openalex-snapshot
Scalable Transformer Accelerator with Variable Systolic Array for Multiple Models in Voice Assistant Applications
inferred← citeshttps://doi.org/10.3390/mi16010101openalex-snapshot
A Low-Power General Matrix Multiplication Accelerator with Sparse Weight-and-Output Stationary Dataflow
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.