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A Composable Monitoring System for Heterogeneous Embedded Platforms
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Reliable Software Technologies – Ada-Europe 2014
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A Novel Run-Time Monitoring Architecture for Safe and Efficient Inline Monitoring
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Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview
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Automated Design Flow for Multi-Functional Dataflow-Based Platforms
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Circularity — a new principle underlying the design of accurate edge orientation operators
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Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)
inferredcites →https://doi.org/10.1016/j.micpro.2018.07.007openalex-snapshot
PowerTap: All-digital power meter modeling for run-time power monitoring
inferredcites →https://doi.org/10.1109/asap.2011.6043237openalex-snapshot
Low-cost hardware profiling of run-time and energy in FPGA embedded processors
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Work-in-Progress: Runtime Requirements Monitoring for State-based Hardware
inferredcites →https://doi.org/10.1109/date.2005.266openalex-snapshot
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
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System-Aware Performance Monitoring Unit for RISC-V Architectures
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Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow
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ZUMA: An Open FPGA Overlay Architecture
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A Survey on FPGA Virtualization
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2009 International Conference on Field-Programmable Technology
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An efficient FPGA-based function profiler for embedded system applications
inferredcites →https://doi.org/10.1109/patmos.2018.8464173openalex-snapshot
FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC
inferredcites →https://doi.org/10.1109/pdp.2016.86openalex-snapshot
A Flexible Profiling Sub-System for Reconfigurable Logic Architectures
inferredcites →https://doi.org/10.1109/reconfig.2018.8641705openalex-snapshot
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
inferredcites →https://doi.org/10.1109/tcad.2016.2565204openalex-snapshot
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits
inferredcites →https://doi.org/10.1109/tcad.2016.2587278openalex-snapshot
A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators
inferredcites →https://doi.org/10.1109/tcad.2016.2614347openalex-snapshot
A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring
inferredcites →https://doi.org/10.1145/2442087.2442088openalex-snapshot
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
inferredcites →https://doi.org/10.1145/2717310openalex-snapshot
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems
inferredcites →https://doi.org/10.1145/3206213openalex-snapshot
Non-Intrusive In-Situ Requirements Monitoring of Embedded System
inferredcites →https://doi.org/10.1145/3310273.3323423openalex-snapshot
Run-time performance monitoring of hardware accelerators
inferredcites →https://doi.org/10.1145/3339861openalex-snapshot
Time-Multiplexed FPGA Overlay Architectures
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The information processing factory
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Efficient Tracing Methodology Using Automata Processor
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Performance Evaluation and Benchmarking
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FPGA Overlays Hardware based Computing for the Masses
inferredcites →https://doi.org/10.23919/date.2017.7927041openalex-snapshot
Performance impacts and limitations of hardware memory access trace collection
inferredcites →https://doi.org/10.3390/s18061877openalex-snapshot
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework
inferredcites →https://doi.org/10.3929/ethz-b-000219249openalex-snapshot
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
inferredcites →https://doi.org/10.5555/3283568.3283575openalex-snapshot
Runtime requirements monitoring for state-based hardware: work-in-progress
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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