On the public citation graph

RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping

https://doi.org/10.1145/3476984
0 signed · 30 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/cvpr.2001.990448openalex-snapshot
Proceedings of the 2001 IEEE Computer Society Conference on Computer Vision and Pattern Recognition. CVPR 2001
inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot
Deep Residual Learning for Image Recognition
inferredcites →https://doi.org/10.1109/cvpr.2018.00474openalex-snapshot
MobileNetV2: Inverted Residuals and Linear Bottlenecks
inferredcites →https://doi.org/10.1109/hpca.2017.29openalex-snapshot
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/hpca47549.2020.00015openalex-snapshot
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training
inferredcites →https://doi.org/10.1109/jetcas.2019.2910232openalex-snapshot
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices
inferredcites →https://doi.org/10.1109/tc.1987.5009457openalex-snapshot
Systolic Arrays for Matrix Transpose and Other Reorderings
inferredcites →https://doi.org/10.1109/tvlsi.2019.2961602openalex-snapshot
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/1390156openalex-snapshot
Proceedings of the 25th international conference on Machine learning - ICML '08
inferredcites →https://doi.org/10.1145/3007787.3001177openalex-snapshot
Eyeriss
inferredcites →https://doi.org/10.1145/30350openalex-snapshot
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3130218.3130230openalex-snapshot
Rethinking NoCs for Spatial Neural Network Accelerators
inferredcites →https://doi.org/10.1145/3173162.3173176openalex-snapshot
MAERI
inferredcites →https://doi.org/10.1145/3297858.3304028openalex-snapshot
Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations
inferredcites →https://doi.org/10.1145/3297858.3304058openalex-snapshot
FA3C
inferredcites →https://doi.org/10.1145/3352460.3358252openalex-snapshot
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow
inferredcites →https://doi.org/10.1145/3352460.3358302openalex-snapshot
Simba
inferredcites →https://doi.org/10.1145/3394885.3431534openalex-snapshot
Accelerate Non-unit Stride Convolutions with Winograd Algorithms

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-19775-8_11openalex-snapshot
U-Boost NAS: Utilization-Boosted Differentiable Neural Architecture Search
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247750openalex-snapshot
Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00067openalex-snapshot
FAST: DNN Training Under Variable Precision Block Floating Point with Stochastic Rounding
inferred← citeshttps://doi.org/10.1109/tc.2024.3449103openalex-snapshot
BiRD: Bi-Directional Input Reuse Dataflow for Enhancing Depthwise Convolution Performance on Systolic Arrays
inferred← citeshttps://doi.org/10.1109/tcad.2022.3198246openalex-snapshot
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2025.3637162openalex-snapshot
Hierarchical-ISA Supporting Row-Wise Operands for Efficient DNN Computation
inferred← citeshttps://doi.org/10.1145/3549937openalex-snapshot
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array
inferred← citeshttps://doi.org/10.1145/3604802openalex-snapshot
A Survey of Design and Optimization for Systolic Array-based DNN Accelerators
inferred← citeshttps://doi.org/10.1145/3620666.3651328openalex-snapshot
TinyForge: A Design Space Exploration to Advance Energy and Silicon Area Trade-offs in tinyML Compute Architectures with Custom Latch Arrays
inferred← citeshttps://doi.org/10.23919/date64628.2025.10992860openalex-snapshot
Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col
inferred← citeshttps://doi.org/10.3390/a17080361openalex-snapshot
Frequency-Domain and Spatial-Domain MLMVN-Based Convolutional Neural Networks
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.