On the public citation graph
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87
0 signed · 67 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9783527697052.ch16openalex-snapshot
Thermal Isolation and Cooling Technologies for Heterogeneous 3D‐ and 2.5D‐ICs
inferred← citeshttps://doi.org/10.1007/978-3-319-07569-3_4openalex-snapshot
Challenges for Migration of Rule-Based Reasoning Engine to a Mobile Platform
inferred← citeshttps://doi.org/10.1007/978-3-642-35843-2_1openalex-snapshot
Theory of Multi Core Hypervisor Verification
inferred← citeshttps://doi.org/10.1016/b978-0-32-390796-5.00013-9openalex-snapshot
Mirrored & hybrid arrays
inferred← citeshttps://doi.org/10.1016/b978-0-32-390796-5.00014-0openalex-snapshot
Redundant Arrays of Independent Disks - RAID
inferred← citeshttps://doi.org/10.1016/b978-0-32-390796-5.00017-6openalex-snapshot
Database parallelism, big data and analytics, deep learning
inferred← citeshttps://doi.org/10.1016/j.cose.2021.102307openalex-snapshot
Timing covert channel analysis of the VxWorks MILS embedded hypervisor under the common criteria security certification
inferred← citeshttps://doi.org/10.1016/j.future.2017.08.007openalex-snapshot
Implications of a metric for performance portability
inferred← citeshttps://doi.org/10.1016/j.jksuci.2017.11.003openalex-snapshot
Energy efficient strategy for placement of virtual machines selected from underloaded servers in compute Cloud
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.12.001openalex-snapshot
Exploiting multi-core nodes in peer-to-peer grids
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.03.014openalex-snapshot
Analyzing fault behavior of shared data in parallel applications
inferred← citeshttps://doi.org/10.1016/j.sysarc.2018.08.006openalex-snapshot
Power optimization techniques for associative processors
inferred← citeshttps://doi.org/10.1016/s0065-2458(00)80004-2openalex-snapshot
Shared memory and distributed shared memory systems: A survey
inferred← citeshttps://doi.org/10.1021/ct400203aopenalex-snapshot
MODYLAS: A Highly Parallelized General-Purpose Molecular Dynamics Simulation Program for Large-Scale Systems with Long-Range Forces Calculated by Fast Multipole Method (FMM) and Highly Scalable Fine-Grained New Parallel Processing Algorithms
inferred← citeshttps://doi.org/10.1103/physreva.108.l060402openalex-snapshot
Enhancing qubit readout with Bayesian learning
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00098openalex-snapshot
Characterizing the Performance of Emerging Deep Learning, Graph, and High Performance Computing Workloads Under Interference
inferred← citeshttps://doi.org/10.1145/1061267.1061269openalex-snapshot
Efficient and flexible architectural support for dynamic monitoring
inferred← citeshttps://doi.org/10.1145/2442087.2442088openalex-snapshot
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
inferred← citeshttps://doi.org/10.1145/2685393openalex-snapshot
Compiler-Directed Power Management for Superscalars
inferred← citeshttps://doi.org/10.1145/279361.279390openalex-snapshot
Options for dynamic address translation in COMAs
inferred← citeshttps://doi.org/10.1145/2882783openalex-snapshot
Improving Resource Efficiency at Scale with Heracles
inferred← citeshttps://doi.org/10.1145/2892242.2892258openalex-snapshot
Performance Implications of Extended Page Tables on Virtualized x86 Processors
inferred← citeshttps://doi.org/10.1145/290409.290411openalex-snapshot
Using value prediction to increase the power of speculative execution hardware
inferred← citeshttps://doi.org/10.1145/3037697.3037724openalex-snapshot
Hardware-Software Co-design to Mitigate DRAM Refresh Overheads
inferred← citeshttps://doi.org/10.1145/3192366.3192392openalex-snapshot
Write-rationing garbage collection for hybrid memories
inferred← citeshttps://doi.org/10.1145/3269982openalex-snapshot
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
inferred← citeshttps://doi.org/10.1145/3296957.3173195openalex-snapshot
Filtering Translation Bandwidth with Virtual Caching
inferred← citeshttps://doi.org/10.1145/3297156.3297201openalex-snapshot
Control Divergence Optimization through Partial Warp Regrouping in GPGPUs
inferred← citeshttps://doi.org/10.1145/3307650.3322236openalex-snapshot
Fine-grained warm water cooling for improving datacenter economy
inferred← citeshttps://doi.org/10.1145/3352460.3358276openalex-snapshot
Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms
inferred← citeshttps://doi.org/10.1145/3374216openalex-snapshot
Informed Prefetching for Indirect Memory Accesses
inferred← citeshttps://doi.org/10.1145/3377149openalex-snapshot
Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding
inferred← citeshttps://doi.org/10.1145/3380732openalex-snapshot
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System
inferred← citeshttps://doi.org/10.1145/3387928openalex-snapshot
Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing
inferred← citeshttps://doi.org/10.1145/3448016.3457236openalex-snapshot
Agile and Accurate CTR Prediction Model Training for Massive-Scale Online Advertising Systems
inferred← citeshttps://doi.org/10.1145/3452099openalex-snapshot
Fast Key-Value Lookups with Node Tracker
inferred← citeshttps://doi.org/10.1145/3468081.3471120openalex-snapshot
Reducing the Repairing Penalty on Misspeculation in Thread-Level Speculation
inferred← citeshttps://doi.org/10.1145/3472883.3487006openalex-snapshot
Provisioning Differentiated Last-Level Cache Allocations to VMs in Public Clouds
inferred← citeshttps://doi.org/10.1145/3476984openalex-snapshot
RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping
inferred← citeshttps://doi.org/10.1145/3548606.3559393openalex-snapshot
Designing Hardware for Cryptography and Cryptography for Hardware
inferred← citeshttps://doi.org/10.1145/3559105openalex-snapshot
FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications
inferred← citeshttps://doi.org/10.1145/3579371.3589068openalex-snapshot
μManycore: A Cloud-Native CPU for Tail at Scale
inferred← citeshttps://doi.org/10.1145/3579371.3589069openalex-snapshot
MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency
inferred← citeshttps://doi.org/10.1145/3579371.3589079openalex-snapshot
Contiguitas: The Pursuit of Physical Memory Contiguity in Datacenters
inferred← citeshttps://doi.org/10.1145/3579371.3589350openalex-snapshot
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings
inferred← citeshttps://doi.org/10.1145/3582016.3582061openalex-snapshot
Heron: Automatically Constrained High-Performance Library Generation for Deep Learning Accelerators
inferred← citeshttps://doi.org/10.1145/3658644.3670319openalex-snapshot
Testing Side-channel Security of Cryptographic Implementations against Future Microarchitectures
inferred← citeshttps://doi.org/10.1145/3663760openalex-snapshot
Multi-Hop Multi-View Memory Transformer for Session-Based Recommendation
inferred← citeshttps://doi.org/10.1145/377769.377780openalex-snapshot
The effect of seance communication on multiprocessing systems
inferred← citeshttps://doi.org/10.1186/s13677-022-00307-4openalex-snapshot
Congestion aware low power on chip protocols with network on chip with cloud security
inferred← citeshttps://doi.org/10.37099/mtu.dc.etdr/589openalex-snapshot
Mitigating the Effect of Misspeculations in Superscalar Processors
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.