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Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices

https://doi.org/10.1145/3477002
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-030-58452-8_13openalex-snapshot
End-to-End Object Detection with Transformers
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Intermittent Inference with Nonuniformly Compressed Multi-Exit Neural Network for Energy Harvesting Powered Devices
inferredcites →https://doi.org/10.1109/iccd50377.2020.00086openalex-snapshot
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inferredcites →https://doi.org/10.1109/tcad.2020.2986127openalex-snapshot
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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
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Structured Pruning of Deep Convolutional Neural Networks
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End-to-End Timing Analysis of Sporadic Cause-Effect Chains in Distributed Systems
inferredcites →https://doi.org/10.1145/3358192openalex-snapshot
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inferredcites →https://doi.org/10.1145/3370748.3406567openalex-snapshot
FTRANS
inferredcites →https://doi.org/10.3390/s21061955openalex-snapshot
Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Hardware and Software Co-optimization for Windows Attention
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ViT Hybrid Channel Fit Pruning Algorithm for Co-optimization of Hardware and Software for Edge Device
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Design of a Modified Transformer Architecture Based on Relative Position Coding
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DRViT: A dynamic redundancy-aware vision transformer accelerator via algorithm and architecture co-design on FPGA
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Survey of FPGA-based accelerators for large language models
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Energy efficient operation of lift control logic using FPGA with two lifts and four floors
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Sub 4-bit Power-of-Two-Based Mixed-Precision Quantization for Efficient LLM Compression and Acceleration
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Hardware-Efficient VLSI Implementation of Self-Attention Transformers for Natural Language Processing
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00027openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071047openalex-snapshot
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Unified Accelerator for Attention and Convolution in Inference Based on FPGA
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043592openalex-snapshot
FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on FPGAs
inferred← citeshttps://doi.org/10.1109/isocc66390.2025.11329964openalex-snapshot
LLM on FPGA: Squeezing Language Models by Quantization and Multi-Query Attention and its Efficient Hardware Architecture
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Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00074openalex-snapshot
ProTEA: Programmable Transformer Encoder Acceleration on FPGA
inferred← citeshttps://doi.org/10.1109/tc.2024.3500362openalex-snapshot
SADIMM: Accelerating Sparse Attention Using DIMM-Based Near-Memory Processing
inferred← citeshttps://doi.org/10.1109/tc.2025.3549621openalex-snapshot
DESA: Dataflow Efficient Systolic Array for Acceleration of Transformers
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197489openalex-snapshot
ViA: A Novel Vision-Transformer Accelerator Based on FPGA
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inferred← citeshttps://doi.org/10.1109/tcsvt.2024.3439600openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tetc.2024.3480524openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3683054openalex-snapshot
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inferred← citeshttps://doi.org/10.1126/science.aef8268openalex-snapshot
Hypervision: An on-chip hyperspectral microsystem for online video-rate computational imaging
inferred← citeshttps://doi.org/10.1145/3489517.3530618openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3549937openalex-snapshot
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array
inferred← citeshttps://doi.org/10.1145/3626202.3637561openalex-snapshot
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
inferred← citeshttps://doi.org/10.1145/3626202.3637569openalex-snapshot
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
inferred← citeshttps://doi.org/10.1145/3634769.3634798openalex-snapshot
REFRESH FPGAs: Sustainable FPGA Chiplet Architectures
inferred← citeshttps://doi.org/10.1145/3635157openalex-snapshot
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices
inferred← citeshttps://doi.org/10.1145/3656177openalex-snapshot
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
inferred← citeshttps://doi.org/10.1145/3662739.3670224openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3690389openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3709026.3709107openalex-snapshot
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TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
inferred← citeshttps://doi.org/10.1145/3797905.3800510openalex-snapshot
DANMP: Accelerating Multi-Scale Deformable Attention Using Near-Memory-Processing Architecture
inferred← citeshttps://doi.org/10.12720/jait.15.10.1163-1173openalex-snapshot
Optimizing Deep Learning Efficiency through Algorithm-Hardware Co-design
inferred← citeshttps://doi.org/10.3390/app132212184openalex-snapshot
Construction of an Online Cloud Platform for Zhuang Speech Recognition and Translation with Edge-Computing-Based Deep Learning Algorithm
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EFA-Trans: An Efficient and Flexible Acceleration Architecture for Transformers
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High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays
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1D-CNN-Transformer for Radar Emitter Identification and Implemented on FPGA
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