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Benzene

https://doi.org/10.1145/3177963
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/date.1998.655828openalex-snapshot
Proceedings Design, Automation and Test in Europe
inferredcites →https://doi.org/10.1109/estimedia.2011.6088521openalex-snapshot
Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache
inferredcites →https://doi.org/10.1109/hotchips.2012.7476487openalex-snapshot
Intel® Xeon Phi coprocessor (codename Knights Corner)
inferredcites →https://doi.org/10.1109/hpca.2009.4798259openalex-snapshot
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
inferredcites →https://doi.org/10.1109/hpca.2011.5749716openalex-snapshot
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
inferredcites →https://doi.org/10.1109/hpca.2011.5749731openalex-snapshot
CloudCache: Expanding and shrinking private caches
inferredcites →https://doi.org/10.1109/hpca.2014.6835933openalex-snapshot
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
inferredcites →https://doi.org/10.1109/hpca.2014.6835944openalex-snapshot
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture
inferredcites →https://doi.org/10.1109/hpca.2015.7056061openalex-snapshot
Scaling distributed cache hierarchies through computation and data co-scheduling
inferredcites →https://doi.org/10.1109/iccd.2007.4601909openalex-snapshot
Cache replacement based on reuse-distance prediction
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2005.52openalex-snapshot
The V-Way Cache: Demand Based Associativity via Global Replacement
inferredcites →https://doi.org/10.1109/isca.2006.5openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1109/isca.2016.19openalex-snapshot
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches
inferredcites →https://doi.org/10.1109/isscc.2008.4523070openalex-snapshot
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/tc.2015.2435772openalex-snapshot
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
inferredcites →https://doi.org/10.1109/tcad.2012.2185930openalex-snapshot
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1080695.1070015openalex-snapshot
The V-Way Cache
inferredcites →https://doi.org/10.1145/1150019.1136501openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1391469.1391610openalex-snapshot
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
inferredcites →https://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferredcites →https://doi.org/10.1145/1555754.1555778openalex-snapshot
PIPP
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/1687399.1687448openalex-snapshot
Energy reduction for STT-RAM using early write termination
inferredcites →https://doi.org/10.1145/2000064.2000073openalex-snapshot
Vantage
inferredcites →https://doi.org/10.1145/2000064.2000074openalex-snapshot
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
inferredcites →https://doi.org/10.1145/2155620.2155659openalex-snapshot
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
inferredcites →https://doi.org/10.1145/2228360.2228406openalex-snapshot
Cache revive
inferredcites →https://doi.org/10.1145/2248418.2248434openalex-snapshot
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache
inferredcites →https://doi.org/10.1145/2333660.2333717openalex-snapshot
Static and dynamic co-optimizations for blocks mapping in hybrid caches
inferredcites →https://doi.org/10.1145/2333660.2333738openalex-snapshot
MAC
inferredcites →https://doi.org/10.1145/2429384.2429401openalex-snapshot
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
inferredcites →https://doi.org/10.1145/2445572.2445577openalex-snapshot
The McPAT Framework for Multicore and Manycore Architectures
inferredcites →https://doi.org/10.1145/2485922.2485963openalex-snapshot
ZSim
inferredcites →https://doi.org/10.1145/2540708.2540735openalex-snapshot
The reuse cache
inferredcites →https://doi.org/10.1145/2627369openalex-snapshot
Proceedings of the 2014 international symposium on Low power electronics and design
inferredcites →https://doi.org/10.1145/3007787.3001148openalex-snapshot
LAP
inferredcites →https://doi.org/10.1145/3559009openalex-snapshot
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1201/b10935openalex-snapshot
Real-Time Embedded Systems
inferredcites →https://doi.org/10.5555/1874620.1874803openalex-snapshot
Power and performance of read-write aware hybrid caches with non-volatile memories
inferredcites →https://doi.org/10.5555/2523721.2523752openalex-snapshot
Jigsaw: scalable software-defined caches
inferredcites →https://doi.org/10.5555/2648668.2648725openalex-snapshot
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring
inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s10617-023-09272-wopenalex-snapshot
Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems
inferred← citeshttps://doi.org/10.1016/j.mejo.2026.107125openalex-snapshot
A Flash acceleration controller that supports redundant replacement
inferred← citeshttps://doi.org/10.1109/access.2020.2972305openalex-snapshot
Statistical Behavior Guided Block Allocation in Hybrid Cache-Based Edge Computing for Cyber-Physical-Social Systems
inferred← citeshttps://doi.org/10.1109/lca.2021.3071717openalex-snapshot
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches
inferred← citeshttps://doi.org/10.1109/recosoc.2018.8449386openalex-snapshot
Exploring Hybrid Memory Caches in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tcad.2019.2912920openalex-snapshot
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
inferred← citeshttps://doi.org/10.1145/3572839openalex-snapshot
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy
inferred← citeshttps://doi.org/10.1587/elex.16.20190358openalex-snapshot
Filter router: An enhanced router design for efficient stacked shared cache network
inferred← citeshttps://doi.org/10.1587/elex.18.20210327openalex-snapshot
Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture
inferred← citeshttps://doi.org/10.3390/electronics8111363openalex-snapshot
Router-Integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems
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