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FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA

https://doi.org/10.1145/3570928
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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U-Net: Convolutional Networks for Biomedical Image Segmentation
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Accelerating the Super-Resolution Convolutional Neural Network
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14th annual design automation conference
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CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes
inferredcites →https://doi.org/10.1109/cvpr.2018.00474openalex-snapshot
MobileNetV2: Inverted Residuals and Linear Bottlenecks
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2012 IEEE Conference on Computer Vision and Pattern Recognition
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2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
inferredcites →https://doi.org/10.1109/fccm53951.2022openalex-snapshot
2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
inferredcites →https://doi.org/10.1109/fpl45767.2018openalex-snapshot
2018 28th International Conference on Field Programmable Logic and Applications (FPL)
inferredcites →https://doi.org/10.1109/fpt46007.2018openalex-snapshot
2018 International Conference on Field-Programmable Technology (FPT)
inferredcites →https://doi.org/10.1109/iccad39534.2017openalex-snapshot
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/icip38660.2017openalex-snapshot
2017 IEEE International Conference on Image Processing (ICIP)
inferredcites →https://doi.org/10.1109/isca41472.2018openalex-snapshot
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
inferredcites →https://doi.org/10.1109/iscas43240.2019openalex-snapshot
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
inferredcites →https://doi.org/10.1109/iscas51556.2021openalex-snapshot
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
inferredcites →https://doi.org/10.1109/isvlsi40576.2017openalex-snapshot
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
inferredcites →https://doi.org/10.1109/micro37956.2016openalex-snapshot
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
inferredcites →https://doi.org/10.1109/tcad.2017.2705069openalex-snapshot
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
inferredcites →https://doi.org/10.1109/tcad.2019.2930577openalex-snapshot
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
inferredcites →https://doi.org/10.1109/tcsii.2018.2865896openalex-snapshot
A CNN Accelerator on FPGA Using Depthwise Separable Convolution
inferredcites →https://doi.org/10.1109/tnnls.2018.2844093openalex-snapshot
fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/tvlsi.2020.2976454openalex-snapshot
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective
inferredcites →https://doi.org/10.1109/tvlsi.2020.2995741openalex-snapshot
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks
inferredcites →https://doi.org/10.1145/3240765.3240801openalex-snapshot
DNNBuilder
inferredcites →https://doi.org/10.1145/3268344openalex-snapshot
PIMap
inferredcites →https://doi.org/10.1145/3400302.3415609openalex-snapshot
DNNExplorer
inferredcites →https://doi.org/10.1145/3431920openalex-snapshot
The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
inferredcites →https://doi.org/10.1145/3603165.3607390openalex-snapshot
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.23919/fpl41764.2017openalex-snapshot
2017 27th International Conference on Field Programmable Logic and Applications (FPL)
inferredcites →https://doi.org/10.3390/electronics10030282openalex-snapshot
FPGA Implementation for CNN-Based Optical Remote Sensing Object Detection
inferredcites →https://doi.org/10.3390/electronics9020286openalex-snapshot
Exploring Efficient Acceleration Architecture for Winograd-Transformed Transposed Convolution of GANs on FPGAs
inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot
Very Deep Convolutional Networks for Large-Scale Image Recognition
inferredcites →https://doi.org/10.48550/arxiv.1511.06434openalex-snapshot
Unsupervised Representation Learning with Deep Convolutional Generative Adversarial Networks
inferredcites →https://doi.org/10.48550/arxiv.1511.07122openalex-snapshot
Multi-Scale Context Aggregation by Dilated Convolutions
inferredcites →https://doi.org/10.48550/arxiv.1603.07285openalex-snapshot
A guide to convolution arithmetic for deep learning
inferredcites →https://doi.org/10.48550/arxiv.1606.02147openalex-snapshot
ENet: A Deep Neural Network Architecture for Real-Time Semantic Segmentation
inferredcites →https://doi.org/10.48550/arxiv.1610.08733openalex-snapshot
GPflow: A Gaussian process library using TensorFlow
inferredcites →https://doi.org/10.48550/arxiv.1704.04861openalex-snapshot
MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9781394336203.ch5openalex-snapshot
Hardware Architectures and Optimization Techniques for Convolutional Neural Network Accelerators
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An Approach to Mitigate CNN Complexity on Domain-Specific Architectures
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Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques
inferred← citeshttps://doi.org/10.1007/s11831-025-10348-yopenalex-snapshot
Optimization Strategies and Algorithms for Accelerating CNN on FPGA: A Comprehensive Review
inferred← citeshttps://doi.org/10.1007/s40010-026-01121-2openalex-snapshot
HLS-Based Resource Optimized High-performance FPGA Implementation of Convolution Layer for CNN Applications
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103113openalex-snapshot
Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs
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BenDan: Benchmarking DPU performance on FPGAs
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High Level Synthesis in the Agentic Era
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Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
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Boosting DNN Efficiency: Replacing FC Layers with Graph Embeddings for Hardware Acceleration
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Towards Resource Efficient and Low Latency CNN Accelerator for FPGAs: Review and Evaluation
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Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming
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SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction
inferred← citeshttps://doi.org/10.1109/fccm62733.2025.00047openalex-snapshot
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
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SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323737openalex-snapshot
SSDe: FPGA-Based SSD Express Emulation Framework
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Automated Design Space Exploration in High-Level Physical Synthesis
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R 2 T-Tiny: Runtime-Reconfigurable Throughput-Optimized TinyML for Hybrid Inference Acceleration on FPGA SoCs
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Mixed Precision Quantized Neural Network Accelerator for Remote Sensing Images Classification
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LHA: Layer-wise Hardware Acceleration of Progressive Quantizing Inference through Partial Reconfiguration for Edge Computing
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ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping
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Instruction-Based Coordination of Heterogeneous Processing Units for Acceleration of DNN Inference
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A High-Intensity Solution of Hardware Accelerator for Sparse and Redundant Computations in Semantic Segmentation Models
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HiTEA-3D: A Design Framework for High-Throughput and Energy-Aware 3D CNN Acceleration on FPGA
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High-Throughput Energy-Efficient Accelerator With Collaborative-Trainable Sparse-Quantization Method for On-Board Remote Sensing Processing
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HCG: Streaming DCNN Accelerator With a Hybrid Computational Granularity Scheme on FPGA
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Accelerating U-Net: A Patchwise Memory Optimization Approach for Image Segmentation
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An FPGA-Based Secure and Privacy-Aware RISC-V SoC with a CNN Accelerator for Edge AI
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Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines
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Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
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A Computation and Energy Efficient Hardware Architecture for SSL Acceleration
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SAT-Accel: A Modern SAT Solver on a FPGA
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Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
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Apiary: An OS for the Modern FPGA
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Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds
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A Design of Network Reconfigurable Universal CNN Accelerator Based on FPGA
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ARCADES: A RISC-V-Coupled Accelerator for Discrete Event Simulation
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