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Exploring Efficient Acceleration Architecture for Winograd-Transformed Transposed Convolution of GANs on FPGAs

https://doi.org/10.3390/electronics9020286

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/cvpr.2016.435openalex-snapshot

Fast Algorithms for Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/fccm.2017.64openalex-snapshot

Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

inferredcites →https://doi.org/10.1109/fccm.2018.00019openalex-snapshot

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks

inferredcites →https://doi.org/10.1109/fpt.2016.7929549openalex-snapshot

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/iccv.2017.252openalex-snapshot

Shape Inpainting Using 3D Generative Adversarial Network and Recurrent Convolutional Networks

inferredcites →https://doi.org/10.1109/icip.2017.8296985openalex-snapshot

ArtGAN: Artwork synthesis with conditional categorical GANs

inferredcites →https://doi.org/10.1109/isca.2018.00060openalex-snapshot

GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks

inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/mm.2015.41openalex-snapshot

A High-Throughput Neural Network Accelerator

inferredcites →https://doi.org/10.1109/tcad.2018.2857258openalex-snapshot

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration

inferredcites →https://doi.org/10.1109/tcsvt.2018.2888898openalex-snapshot

An Energy-Efficient FPGA-Based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolution

inferredcites →https://doi.org/10.1109/tvlsi.2018.2815603openalex-snapshot

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot

An OpenCL™ Deep Learning Accelerator on Arria 10

inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot

Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

inferredcites →https://doi.org/10.1145/3065386openalex-snapshot

ImageNet classification with deep convolutional neural networks

inferredcites →https://doi.org/10.1145/3343031.3350944openalex-snapshot

GP-GAN

inferredcites →https://doi.org/10.21437/interspeech.2016-1446openalex-snapshot

Towards End-to-End Speech Recognition with Deep Convolutional Neural Networks

inferredcites →https://doi.org/10.3390/electronics8010065openalex-snapshot

A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs

inferredcites →https://doi.org/10.48550/arxiv.1406.2661openalex-snapshot

Generative Adversarial Networks

inferredcites →https://doi.org/10.48550/arxiv.1610.07584openalex-snapshot

Learning a Probabilistic Latent Space of Object Shapes via 3D Generative-Adversarial Modeling

inferredcites →https://doi.org/10.48550/arxiv.1703.05192openalex-snapshot

Learning to Discover Cross-Domain Relations with Generative Adversarial Networks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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FPGA Implementation of Column-Wise Deconvolution Accelerator Based on Structural Optimization for Medical Image Segmentation

inferred← citeshttps://doi.org/10.1007/s11265-023-01883-7openalex-snapshot

FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis

inferred← citeshttps://doi.org/10.1016/j.applthermaleng.2021.117836openalex-snapshot

Numerical investigation on thermal-hydraulic characteristics of the micro heat sink with gradient distribution pin fin arrays and narrow slots

inferred← citeshttps://doi.org/10.1016/j.icte.2025.10.015openalex-snapshot

Advancements in neural network acceleration: a comprehensive review

inferred← citeshttps://doi.org/10.1109/access.2024.3397536openalex-snapshot

Energy-Efficient Implementation of YOLOv8, Instance Segmentation, and Pose Detection on RISC-V SoC

inferred← citeshttps://doi.org/10.1109/access.2024.3413038openalex-snapshot

A Comprehensive Exploration of L-UNet Approach: Revolutionizing Medical Image Segmentation

inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786198openalex-snapshot

A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA

inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00049openalex-snapshot

Accelerating Transposed Convolutions on FPGA-Based Edge Devices

inferred← citeshttps://doi.org/10.1109/hipc53243.2021.00022openalex-snapshot

How to Avoid Zero-Spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-Design Methodology

inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937301openalex-snapshot

A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm

inferred← citeshttps://doi.org/10.1109/jetcas.2025.3575272openalex-snapshot

Generative AI Through CAS Lens: An Integrated Overview of Algorithmic Optimizations, Architectural Advances, and Automated Designs

inferred← citeshttps://doi.org/10.1109/tnnls.2021.3110728openalex-snapshot

FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm

inferred← citeshttps://doi.org/10.1109/vdat72243.2026.11704568openalex-snapshot

A Comparative Analysis of PE Architectures for CNN Accelerators

inferred← citeshttps://doi.org/10.1145/3570928openalex-snapshot

FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA

inferred← citeshttps://doi.org/10.1145/3641584.3641684openalex-snapshot

A Reconfigurable GC-CycleGAN Based on Convolutional Optimization

inferred← citeshttps://doi.org/10.11591/ijece.v11i5.pp4221-4232openalex-snapshot

High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications

inferred← citeshttps://doi.org/10.22399/ijcesen.2557openalex-snapshot

The Adaptive Consumer: Social Media, Q-Commerce, and Dark Warehouses Drive Purchase Flexibility in Indian Cities

inferred← citeshttps://doi.org/10.3390/app122110771openalex-snapshot

A Review of the Optimal Design of Neural Networks Based on FPGA

inferred← citeshttps://doi.org/10.3390/electronics9111789openalex-snapshot

New Applications and Architectures Based on FPGA/SoC

inferred← citeshttps://doi.org/10.3390/jimaging6090085openalex-snapshot

Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip

inferred← citeshttps://doi.org/10.3390/jimaging7100210openalex-snapshot

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

inferred← citeshttps://doi.org/10.5772/intechopen.1007291openalex-snapshot

Efficient DNN Algorithm Design and Hardware Acceleration for Low-Level Vision

inferred← citeshttps://doi.org/10.7287/peerj-cs.973v0.1/reviews/1openalex-snapshot

Peer Review #1 of "FPGA-based systolic deconvolution architecture for upsampling (v0.1)"

inferred← citeshttps://doi.org/10.7287/peerj-cs.973v0.1/reviews/2openalex-snapshot

Peer Review #2 of "FPGA-based systolic deconvolution architecture for upsampling (v0.1)"

inferred← citeshttps://doi.org/10.7287/peerj-cs.973v0.1/reviews/3openalex-snapshot

Peer Review #3 of "FPGA-based systolic deconvolution architecture for upsampling (v0.1)"

inferred← citeshttps://doi.org/10.7717/peerj-cs.973openalex-snapshot

FPGA-based systolic deconvolution architecture for upsampling

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