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High-Level Approaches to Hardware Security: A Tutorial
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-03515-4_6openalex-snapshot
Improved Scan-Chain Based Attacks and Related Countermeasures
inferredcites →https://doi.org/10.1007/978-3-319-13039-2_11openalex-snapshot
Cryptanalysis of the Double-Feedback XOR-Chain Scheme Proposed in Indocrypt 2013
inferredcites →https://doi.org/10.1007/978-3-540-89754-5_18openalex-snapshot
Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures
inferredcites →https://doi.org/10.1007/978-3-642-81955-1_28openalex-snapshot
On the Complexity of Derivation in Propositional Calculus
inferredcites →https://doi.org/10.1016/j.iot.2019.100055openalex-snapshot
A comprehensive survey of hardware-assisted security: From the edge to the cloud
inferredcites →https://doi.org/10.1016/j.istr.2009.06.001openalex-snapshot
Attacking smart card systems: Theory and practice
inferredcites →https://doi.org/10.1016/j.vlsi.2016.10.011openalex-snapshot
Why current secure scan designs fail and how to fix them?
inferredcites →https://doi.org/10.1090/dimacs/035/02openalex-snapshot
Algorithms for the satisfiability (SAT) problem: A survey
inferredcites →https://doi.org/10.1109/access.2021.3080257openalex-snapshot
From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains
inferredcites →https://doi.org/10.1109/asianhost53231.2021.9699758openalex-snapshot
From FPGAs to Obfuscated eASICs: Design and Security Trade-offs
inferredcites →https://doi.org/10.1109/cases.2018.8516874openalex-snapshot
Special Session: Advances and Throwbacks in Hardware-Assisted Security
inferredcites →https://doi.org/10.1109/cases44625.2018openalex-snapshot
2018 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)
inferredcites →https://doi.org/10.1109/dac18074.2021openalex-snapshot
2021 58th ACM/IEEE Design Automation Conference (DAC)
inferredcites →https://doi.org/10.1109/date.1998.655868openalex-snapshot
Functional scan chain testing
inferredcites →https://doi.org/10.1109/ets.2014.6847798openalex-snapshot
Test-mode-only scan attack using the boundary scan chain
inferredcites →https://doi.org/10.1109/hst.2015.7140252openalex-snapshot
Evaluating the security of logic encryption algorithms
inferredcites →https://doi.org/10.1109/hst.2017.7951805openalex-snapshot
AppSAT: Approximately deobfuscating integrated circuits
inferredcites →https://doi.org/10.1109/iccad.2017.8203759openalex-snapshot
CycSAT: SAT-based attack on cyclic logic encryptions
inferredcites →https://doi.org/10.1109/iccad45719.2019.8942077openalex-snapshot
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/iccad51958.2021openalex-snapshot
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
inferredcites →https://doi.org/10.1109/ieeestd.2013.6515989openalex-snapshot
IEEE Standard for Test Access Port and Boundary-Scan Architecture
inferredcites →https://doi.org/10.1109/isca.2014.6853210openalex-snapshot
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
inferredcites →https://doi.org/10.1109/isocc.2012.6407063openalex-snapshot
Dynamically changeable secure scan architecture against scan-based side channel attack
inferredcites →https://doi.org/10.1109/isqed54688.2022.9806254openalex-snapshot
Challenges and Opportunities for Hardware-Assisted Security Improvements in the Field
inferredcites →https://doi.org/10.1109/isvlsi.2019.00118openalex-snapshot
Towards Hardware-Assisted Security for IoT Systems
inferredcites →https://doi.org/10.1109/itc-asia.2019.00030openalex-snapshot
Characterization of Locked Sequential Circuits via ATPG
inferredcites →https://doi.org/10.1109/itc41524.2018openalex-snapshot
2018 IEEE International Test Conference (ITC)
inferredcites →https://doi.org/10.1109/jproc.2014.2325397openalex-snapshot
Microcontrollers as (In)Security Devices for Pervasive Computing Applications
inferredcites →https://doi.org/10.1109/jproc.2014.2335155openalex-snapshot
A Primer on Hardware Security: Models, Methods, and Metrics
inferredcites →https://doi.org/10.1109/msec.2020.2990230openalex-snapshot
Dedicated Security Chips in the Age of Secure Enclaves
inferredcites →https://doi.org/10.1109/olt.2004.1319691openalex-snapshot
Scan design and secure chip [secure IC testing]
inferredcites →https://doi.org/10.1109/tcad.2005.862745openalex-snapshot
Secure Scan: A Design-for-Test Architecture for Crypto Chips
inferredcites →https://doi.org/10.1109/tcad.2007.906483openalex-snapshot
Secured Flipped Scan-Chain Model for Crypto-Architecture
inferredcites →https://doi.org/10.1109/tcad.2009.2028166openalex-snapshot
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
inferredcites →https://doi.org/10.1109/tcad.2019.2944586openalex-snapshot
Keynote: A Disquisition on Logic Locking
inferredcites →https://doi.org/10.1109/tcad.2020.2968898openalex-snapshot
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
inferredcites →https://doi.org/10.1109/tcad.2020.3029133openalex-snapshot
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking
inferredcites →https://doi.org/10.1109/tcsii.2019.2915606openalex-snapshot
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits
inferredcites →https://doi.org/10.1109/test.2004.1386969openalex-snapshot
Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard
inferredcites →https://doi.org/10.1109/tetc.2019.2940750openalex-snapshot
ScanSAT: Unlocking Static and Dynamic Scan Obfuscation
inferredcites →https://doi.org/10.1109/tifs.2021.3096028openalex-snapshot
SAIL: Analyzing Structural Artifacts of Logic Locking Using Machine Learning
inferredcites →https://doi.org/10.1109/tvlsi.2018.2797019openalex-snapshot
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
inferredcites →https://doi.org/10.1109/tvlsi.2021.3089555openalex-snapshot
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking
inferredcites →https://doi.org/10.1109/tvlsi.2023.3307027openalex-snapshot
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
inferredcites →https://doi.org/10.1109/vlsi-soc54400.2022openalex-snapshot
2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
inferredcites →https://doi.org/10.1109/vts.2017.7928947openalex-snapshot
Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain
inferredcites →https://doi.org/10.1145/3060403.3060458openalex-snapshot
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits
inferredcites →https://doi.org/10.1145/3133956.3133985openalex-snapshot
Provably-Secure Logic Locking
inferredcites →https://doi.org/10.1145/3431389openalex-snapshot
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
inferredcites →https://doi.org/10.1145/3531437.3539728openalex-snapshot
Predictive Model Attack for Embedded FPGA Logic Locking
inferredcites →https://doi.org/10.1145/3549206.3549235openalex-snapshot
Obviating Multiple Attacks with Enhanced Logic Locking
inferredcites →https://doi.org/10.1145/996566.996771openalex-snapshot
Security as a new dimension in embedded system design
inferredcites →https://doi.org/10.23919/date.2019.8714856openalex-snapshot
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming
inferredcites →https://doi.org/10.23919/date.2019.8715053openalex-snapshot
KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation
inferredcites →https://doi.org/10.23919/date42667.2018openalex-snapshot
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
inferredcites →https://doi.org/10.46586/tches.v2022.i2.92-114openalex-snapshot
Towards a Formal Treatment of Logic Locking
inferredcites →https://doi.org/10.6028/nist.fips.197openalex-snapshot
Advanced Encryption Standard (AES)
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-032-15576-4_24openalex-snapshot
Toward Cybersecure-by-Design Manufacturing Systems: A Taxonomy of Hardware-Based Approaches for Software Cybersecurity Violation Detection
inferred← citeshttps://doi.org/10.1007/978-981-97-3756-7_16openalex-snapshot
LightLock: Ensuring Hardware IP Security in IoT Environment with Lightweight Logic Locking
inferred← citeshttps://doi.org/10.1049/cdt2/5926846openalex-snapshot
Watermarking of Transient Fault‐Detectable IP Designs Using Multivariate HLS Scheduling Based Multimodal Security
inferred← citeshttps://doi.org/10.1109/admit67050.2025.11336831openalex-snapshot
Incremental Compilation-Based Clock Margin Optimization for FPGA
inferred← citeshttps://doi.org/10.1109/apccas60141.2023.00030openalex-snapshot
LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133104openalex-snapshot
Identifying System-on-Chip Security Assets with Structure-Based Analysis
inferred← citeshttps://doi.org/10.1109/icce-taiwan62264.2024.10674266openalex-snapshot
HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN
inferred← citeshttps://doi.org/10.1109/icce-taiwan71481.2026.11652837openalex-snapshot
Integrated Hardware Watermarking Framework Based on 3-Factor Encoding, Connectivity Matrix and Hashing for Securing Sharpening Filter IP Cores Against Piracy
inferred← citeshttps://doi.org/10.1109/les.2025.3614187openalex-snapshot
HLS Trojan Detection Using Machine Learning Technique
inferred← citeshttps://doi.org/10.1109/socc66126.2025.11235474openalex-snapshot
Secure Optimized Hardware IP Design using Key-driven Hash Slicing based HLS Watermarking Integrated with Krill-Herd DSE
inferred← citeshttps://doi.org/10.1109/techdefense67306.2025.11721043openalex-snapshot
Review on hardware logical encryption
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3307027openalex-snapshot
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
inferred← citeshttps://doi.org/10.1142/s0219581x26400284openalex-snapshot
Emerging Device-Based Hardware Security Primitives: From CMOS PUFs to Ferroelectric and Memristive Technologies
inferred← citeshttps://doi.org/10.1145/3709139openalex-snapshot
SRLL: Improving Security and Reliability with User-Defined Constraint-Aware Logic Locking
inferred← citeshttps://doi.org/10.1145/3758321openalex-snapshot
Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539092openalex-snapshot
LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
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