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A compiler approach for reducing data cache energy
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01130405openalex-snapshot
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design
inferredcites →https://doi.org/10.1109/2.546613openalex-snapshot
Maximizing multiprocessor performance with the SUIF compiler
inferredcites →https://doi.org/10.1109/4.400426openalex-snapshot
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
inferredcites →https://doi.org/10.1109/4.871328openalex-snapshot
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current
inferredcites →https://doi.org/10.1109/92.920821openalex-snapshot
Reducing leakage in a high-performance deep-submicron instruction cache
inferredcites →https://doi.org/10.1109/9780470544365openalex-snapshot
Design of High-Performance Microprocessor Circuits
inferredcites →https://doi.org/10.1109/hicss.1996.495462openalex-snapshot
Improving software pipelining with unroll-and-jam
inferredcites →https://doi.org/10.1109/iccd.2001.955040openalex-snapshot
Static energy reduction techniques for microprocessor caches
inferredcites →https://doi.org/10.1109/ipps.1994.288280openalex-snapshot
Optimal software pipelining of nested loops
inferredcites →https://doi.org/10.1109/tvlsi.2003.812370openalex-snapshot
Static energy reduction techniques for microprocessor caches
inferredcites →https://doi.org/10.1109/vlsic.1998.687996openalex-snapshot
A new technique for standby leakage reduction in high-performance circuits
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/125826.125893openalex-snapshot
Tiling multidimensional iteration spaces for nonshared memory machines
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/178243.178247openalex-snapshot
VLIW compilation techniques in a superscalar environment
inferredcites →https://doi.org/10.1145/201059.201065openalex-snapshot
Supporting dynamic data structures on distributed-memory machines
inferredcites →https://doi.org/10.1145/237090.237190openalex-snapshot
Compiler-based prefetching for recursive data structures
inferredcites →https://doi.org/10.1145/267959.269966openalex-snapshot
Parallelizing nonnumerical code with selective scheduling and software pipelining
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/277650.277661openalex-snapshot
Data transformations for eliminating conflict misses
inferredcites →https://doi.org/10.1145/335043.335044openalex-snapshot
System-level power optimization
inferredcites →https://doi.org/10.1145/360128.360148openalex-snapshot
A static power model for architects
inferredcites →https://doi.org/10.1145/360128.360153openalex-snapshot
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/545214.545231openalex-snapshot
Dynamic fine-grain leakage reduction using leakage-biased bitlines
inferredcites →https://doi.org/10.5555/563998.564012openalex-snapshot
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
inferredcites →https://doi.org/10.5555/645988.674162openalex-snapshot
Adaptive Mode Control: A Static-Power-Efficient Cache Design
inferredcites →https://doi.org/10.5555/645989.674306openalex-snapshot
Leakage energy management in cache hierarchies
inferredcites →https://doi.org/10.5555/774861.774884openalex-snapshot
Compiler-directed instruction cache leakage optimization
inferredcites →https://doi.org/10.5555/774861.774885openalex-snapshot
Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11572961_60openalex-snapshot
Cache Leakage Management for Multi-programming Workloads
inferred← citeshttps://doi.org/10.1016/j.micpro.2009.02.003openalex-snapshot
Hardware–compiler co-design for adjustable data power savings
inferred← citeshttps://doi.org/10.1016/j.suscom.2013.11.001openalex-snapshot
A survey of architectural techniques for improving cache power efficiency
inferred← citeshttps://doi.org/10.1016/s0065-2458(06)69003-7openalex-snapshot
Compiler-Assisted Leakage Energy Reduction for Cache Memories
inferred← citeshttps://doi.org/10.1049/ip-cdt:20045059openalex-snapshot
Leakage-aware compilation for VLIW architectures
inferred← citeshttps://doi.org/10.1109/cgo.2011.5764672openalex-snapshot
Link-time optimization for power efficiency in a tagless instruction cache
inferred← citeshttps://doi.org/10.1109/ipdps.2005.404openalex-snapshot
Software-Directed Disk Power Management for Scientific Applications
inferred← citeshttps://doi.org/10.1109/isvlsi.2004.1339566openalex-snapshot
Compiler-directed data cache leakage reduction
inferred← citeshttps://doi.org/10.1109/pccc.2007.358916openalex-snapshot
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization
inferred← citeshttps://doi.org/10.1109/pdp.2016.39openalex-snapshot
Energy-Aware Programming Model for Distributed Infrastructures
inferred← citeshttps://doi.org/10.1109/tc.2011.44openalex-snapshot
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1145/1057661.1057727openalex-snapshot
Energy management in software-controlled multi-level memory hierarchies
inferred← citeshttps://doi.org/10.1145/1108956.1108957openalex-snapshot
Power reduction techniques for microprocessor systems
inferred← citeshttps://doi.org/10.1145/997163.997178openalex-snapshot
A trace-based binary compilation framework for energy-aware computing
inferred← citeshttps://doi.org/10.1145/998300.997178openalex-snapshot
A trace-based binary compilation framework for energy-aware computing
inferred← citeshttps://doi.org/10.1201/9781420043839.ch7openalex-snapshot
Energy-Aware Compiler Optimizations
inferred← citeshttps://doi.org/10.3233/emc-2005-00049openalex-snapshot
Exploiting loop behavior for data cache leakage reduction
inferred← citeshttps://doi.org/10.70675/ce7fc6e7zd0d3z49adzb943z5b499271e150openalex-snapshot
Conception d'algorithmes hybrides pour l'optimisation de l'énergie mémoire dans les systèmes embarqués et de fonctions multimodales
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