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https://doi.org/10.1145/782837.782838
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/asap.2006.30openalex-snapshot
Efficient Group KeyManagement with Tamper-resistant ISA Extensions
inferred← citeshttps://doi.org/10.1109/cloudcom.2013.55openalex-snapshot
A Framework for Realizing Security on Demand in Cloud Computing
inferred← citeshttps://doi.org/10.1109/csac.2004.25openalex-snapshot
Open-Source Applications of TCPA Hardware
inferred← citeshttps://doi.org/10.1109/csie.2009.45openalex-snapshot
A New Method to Protect Software from Cracking
inferred← citeshttps://doi.org/10.1109/date.2005.170openalex-snapshot
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
inferred← citeshttps://doi.org/10.1109/date.2005.266openalex-snapshot
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
inferred← citeshttps://doi.org/10.1109/date.2007.364391openalex-snapshot
Microarchitectural Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors
inferred← citeshttps://doi.org/10.1109/date.2008.4484834openalex-snapshot
Operating System Controlled Processor-Memory Bus Encryption
inferred← citeshttps://doi.org/10.1109/ddecs.2006.1649595openalex-snapshot
PE-ICE: Parallelized Encryption and Integrity Checking Engine
inferred← citeshttps://doi.org/10.1109/dfma.2005.17openalex-snapshot
Conditional Access in Mobile Systems: Securing the Application
inferred← citeshttps://doi.org/10.1109/hicss.2006.114openalex-snapshot
Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms
inferred← citeshttps://doi.org/10.1109/hpca.2006.1598131openalex-snapshot
InfoShield: A Security Architecture for Protecting Information Usage in Memory
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835931openalex-snapshot
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835932openalex-snapshot
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071130openalex-snapshot
Efficient Distributed Secure Memory with Migratable Merkle Tree
inferred← citeshttps://doi.org/10.1109/hpec.2013.6670339openalex-snapshot
Integrity verification for path Oblivious-RAM
inferred← citeshttps://doi.org/10.1109/icebe.2011.69openalex-snapshot
User Centric Security Model for Tamper-Resistant Devices
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.187openalex-snapshot
Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture
inferred← citeshttps://doi.org/10.1109/isca.2004.1310777openalex-snapshot
iWatcher: efficient architectural support for software debugging
inferred← citeshttps://doi.org/10.1109/isca.2005.14openalex-snapshot
Architecture for Protecting Critical Secrets in Microprocessors
inferred← citeshttps://doi.org/10.1109/isca.2005.30openalex-snapshot
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
inferred← citeshttps://doi.org/10.1109/jetcas.2014.2372431openalex-snapshot
Reconfiguration-Based VLSI Design for Security
inferred← citeshttps://doi.org/10.1109/micro.2004.26openalex-snapshot
Minos: Control Data Attack Prevention Orthogonal to Memory Model
inferred← citeshttps://doi.org/10.1109/micro.2004.31openalex-snapshot
RIFLE: An Architectural Framework for User-Centric Information-Flow Security
inferred← citeshttps://doi.org/10.1109/micro.2008.4771783openalex-snapshot
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits
inferred← citeshttps://doi.org/10.1109/mpot.2008.930448openalex-snapshot
Surveying secure processors
inferred← citeshttps://doi.org/10.1109/pact.2004.1342547openalex-snapshot
Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems
inferred← citeshttps://doi.org/10.1109/recosoc.2012.6322896openalex-snapshot
Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system
inferred← citeshttps://doi.org/10.1109/rme.2006.1689972openalex-snapshot
How to Add the Integrity Checking Capability to Block Encryption Algorithms
inferred← citeshttps://doi.org/10.1109/sbac-pad.2004.17openalex-snapshot
FlowCert : Probabilistic Certification for Peer-to-Peer Computations
inferred← citeshttps://doi.org/10.1109/sp.2005.2openalex-snapshot
A Generic Attack on Checksumming-Based Software Tamper Resistance
inferred← citeshttps://doi.org/10.1109/sp.2005.24openalex-snapshot
Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data
inferred← citeshttps://doi.org/10.1109/spl.2007.371757openalex-snapshot
Bus Decryption Overhead Minimization with Code Compression
inferred← citeshttps://doi.org/10.1109/tc.2011.60openalex-snapshot
Scalable Web Content Attestation
inferred← citeshttps://doi.org/10.1109/tdsc.2005.24openalex-snapshot
Hardware-Assisted Circumvention of Self-Hashing Software Tamper Resistance
inferred← citeshttps://doi.org/10.1109/tii.2010.2068303openalex-snapshot
A Flexible Design Flow for Software IP Binding in FPGA
inferred← citeshttps://doi.org/10.1109/tr.2015.2430471openalex-snapshot
Fingerprint-Based Detection and Diagnosis of Malicious Programs in Hardware
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.887799openalex-snapshot
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2007.896913openalex-snapshot
Architectural Support for Run-Time Validation of Program Data Properties
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2025765openalex-snapshot
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors
inferred← citeshttps://doi.org/10.2200/s00864ed1v01y201807cac045openalex-snapshot
Principles of Secure Processor Architecture Design
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.530-531.631openalex-snapshot
A New Hardware Isolation Architecture
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amr.488-489.1480openalex-snapshot
Research on Hardware Security of Embedded System in Cloud Environment
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