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A Novel Cu Filling Method for High-Aspect-Ratio (Ar) Nano-Scale Tsvs

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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/j.apsusc.2015.10.214openalex-snapshot

Wetting process of copper filling in through silicon vias

inferredcites →https://doi.org/10.1016/j.mee.2015.04.096openalex-snapshot

Optimization of through silicon via for three-dimensional integration

inferredcites →https://doi.org/10.1021/jp034875mopenalex-snapshot

Inhibition Due to the Interaction of Polyethylene Glycol, Chloride, and Copper in Plating Baths: A Surface-Enhanced Raman Study

inferredcites →https://doi.org/10.1108/ssmt-04-2013-0011openalex-snapshot

Cu filling of TSV using various current forms for three‐dimensional packaging application

inferredcites →https://doi.org/10.1109/3dic48104.2019.9058895openalex-snapshot

3D Integration Technologies for the Stacked CMOS Image Sensors

inferredcites →https://doi.org/10.1109/ectc.2011.5898776openalex-snapshot

Evaluation of additives and current mode on copper via filling

inferredcites →https://doi.org/10.1109/ectc.2012.6248928openalex-snapshot

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

inferredcites →https://doi.org/10.1109/ectc32862.2020.00020openalex-snapshot

Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

inferredcites →https://doi.org/10.1109/ectc51529.2024.00166openalex-snapshot

Block level and package level thermal assessment for back side power delivery network.

inferredcites →https://doi.org/10.1109/ectc51529.2024.00258openalex-snapshot

Electrical Characterization and Reliability Studies of Nano-TSV

inferredcites →https://doi.org/10.1109/icept-hdp.2012.6474664openalex-snapshot

Copper filling process for small diameter, high aspect ratio Through Silicon Via (TSV)

inferredcites →https://doi.org/10.1109/iedm45625.2022.10019349openalex-snapshot

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network

inferredcites →https://doi.org/10.1109/irps48228.2024.10529350openalex-snapshot

Self-Heating Effect of Device-Circuit with Back-side Power Delivery Network beyond 3nm Node

inferredcites →https://doi.org/10.1109/tcpmt.2014.2298031openalex-snapshot

TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

inferredcites →https://doi.org/10.1145/3219617.3219659openalex-snapshot

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

inferredcites →https://doi.org/10.1145/3224432openalex-snapshot

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

inferredcites →https://doi.org/10.23919/vlsicircuits52068.2021.9492421openalex-snapshot

Design and Technology Solutions for 3D Integrated High Performance Systems

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