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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations
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Improving the reliability of chip-off forensic analysis of NAND flash memory devices
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Tunable Charge-Trap Memory Based on Few-Layer MoS2
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On the retention time distribution of dynamic random access memory (DRAM)
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A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
inferredcites →https://doi.org/10.1109/55.998871openalex-snapshot
Effects of floating-gate interference on NAND flash memory cell operation
inferredcites →https://doi.org/10.1109/date.2012.6176524openalex-snapshot
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis
inferredcites →https://doi.org/10.1109/dsn.2015.49openalex-snapshot
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
inferredcites →https://doi.org/10.1109/dsn.2015.58openalex-snapshot
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
inferredcites →https://doi.org/10.1109/dsn.2016.30openalex-snapshot
PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM
inferredcites →https://doi.org/10.1109/fccm.2011.28openalex-snapshot
FPGA-Based Solid-State Drive Prototyping Platform
inferredcites →https://doi.org/10.1109/glocom.2014.7037159openalex-snapshot
Modelling of the threshold voltage distributions of sub-20nm NAND flash memory
inferredcites →https://doi.org/10.1109/hpca.2012.6168954openalex-snapshot
Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications
inferredcites →https://doi.org/10.1109/hpca.2015.7056057openalex-snapshot
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
inferredcites →https://doi.org/10.1109/hpca.2015.7056062openalex-snapshot
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery
inferredcites →https://doi.org/10.1109/hpca.2017.61openalex-snapshot
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques
inferredcites →https://doi.org/10.1109/hpca.2017.62openalex-snapshot
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
inferredcites →https://doi.org/10.1109/hpca.2018.00026openalex-snapshot
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
inferredcites →https://doi.org/10.1109/hpca.2018.00050openalex-snapshot
HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness
inferredcites →https://doi.org/10.1109/iccd.2012.6378623openalex-snapshot
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
inferredcites →https://doi.org/10.1109/iccd.2013.6657034openalex-snapshot
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation
inferredcites →https://doi.org/10.1109/iedm.1988.32846openalex-snapshot
Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness
inferredcites →https://doi.org/10.1109/iedm.2010.5703304openalex-snapshot
Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash
inferredcites →https://doi.org/10.1109/iedm.2012.6478964openalex-snapshot
Origin of transient Vth shift after erase and its impact on 2D/3D structure charge trap flash memory cell operations
inferredcites →https://doi.org/10.1109/imw.2017.7939077openalex-snapshot
Data-Retention Characteristics Comparison of 2D and 3D TLC NAND Flash Memories
inferredcites →https://doi.org/10.1109/isca.2012.6237001openalex-snapshot
RAIDR: Retention-aware intelligent DRAM refresh
inferredcites →https://doi.org/10.1109/isscc.2012.6177075openalex-snapshot
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers
inferredcites →https://doi.org/10.1109/isscc.2015.7062960openalex-snapshot
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
inferredcites →https://doi.org/10.1109/isscc.2016.7417941openalex-snapshot
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
inferredcites →https://doi.org/10.1109/isscc.2016.7417945openalex-snapshot
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate
inferredcites →https://doi.org/10.1109/jproc.2003.811702openalex-snapshot
Introduction to flash memory
inferredcites →https://doi.org/10.1109/jsac.2016.2603608openalex-snapshot
Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory
inferredcites →https://doi.org/10.1109/jssc.2014.2352293openalex-snapshot
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming
inferredcites →https://doi.org/10.1109/jssc.2015.2413841openalex-snapshot
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations
inferredcites →https://doi.org/10.1109/jssc.2017.2731813openalex-snapshot
A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
inferredcites →https://doi.org/10.1109/lca.2016.2624298openalex-snapshot
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM
inferredcites →https://doi.org/10.1109/led.2009.2026658openalex-snapshot
Random Telegraph Noise Effect on the Programmed Threshold-Voltage Distribution of Flash Memories
inferredcites →https://doi.org/10.1109/mascots.2014.37openalex-snapshot
ZombieNAND: Resurrecting Dead NAND Flash for Improved SSD Longevity
inferredcites →https://doi.org/10.1109/mdat.2017.2705144openalex-snapshot
A Platform to Analyze DDR3 DRAM’s Power and Retention Time
inferredcites →https://doi.org/10.1109/msst.2015.7208284openalex-snapshot
WARM: Improving NAND flash memory lifetime with write-hotness aware retention management
inferredcites →https://doi.org/10.1109/patmos.2016.7833700openalex-snapshot
A new bank sensitive DRAMPower model for efficient design space exploration
inferredcites →https://doi.org/10.1109/relphy.2008.4558857openalex-snapshot
Bit error rate in NAND Flash memories
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An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory
inferredcites →https://doi.org/10.1109/ted.2004.833583openalex-snapshot
Analytical Percolation Model for Predicting Anomalous Charge Loss in Flash Memories
inferredcites →https://doi.org/10.1109/ted.2009.2024031openalex-snapshot
Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories
inferredcites →https://doi.org/10.1109/ted.2010.2088126openalex-snapshot
Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String
inferredcites →https://doi.org/10.1109/tit.1981.1056312openalex-snapshot
High-speed decoding of BCH codes (Corresp.)
inferredcites →https://doi.org/10.1109/vlsic.2007.4342709openalex-snapshot
A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond
inferredcites →https://doi.org/10.1109/vlsit.2016.7573385openalex-snapshot
Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory
inferredcites →https://doi.org/10.1145/2485922.2485928openalex-snapshot
An experimental study of data retention behavior in modern DRAM devices
inferredcites →https://doi.org/10.1145/2500727.2500743openalex-snapshot
A read-disturb management technique for high-density NAND flash memory
inferredcites →https://doi.org/10.1145/2508148.2485928openalex-snapshot
An experimental study of data retention behavior in modern DRAM devices
inferredcites →https://doi.org/10.1145/2591513.2591594openalex-snapshot
Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems
inferredcites →https://doi.org/10.1145/2591971.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/2597652.2597681openalex-snapshot
Understanding the impact of threshold voltage on MLC flash memory performance and reliability
inferredcites →https://doi.org/10.1145/2637364.2591994openalex-snapshot
Neighbor-cell assisted error correction for MLC NAND flash memories
inferredcites →https://doi.org/10.1145/2637364.2592000openalex-snapshot
The efficacy of error mitigation techniques for DRAM retention failures
inferredcites →https://doi.org/10.1145/2678373.2665726openalex-snapshot
Flipping bits in memory without accessing them
inferredcites →https://doi.org/10.1145/2796314.2745848openalex-snapshot
A Large-Scale Study of Flash Memory Failures in the Field
inferredcites →https://doi.org/10.1145/2896377.2901453openalex-snapshot
Understanding Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/2897937.2898032openalex-snapshot
Improving performance and lifetime of NAND storage systems using relaxed program sequence
inferredcites →https://doi.org/10.1145/3078505.3078533openalex-snapshot
Design-Induced Latency Variation in Modern DRAM Chips
inferredcites →https://doi.org/10.1145/3078505.3078550openalex-snapshot
Characterizing 3D Floating Gate NAND Flash
inferredcites →https://doi.org/10.1145/3078505.3078590openalex-snapshot
Understanding Reduced-Voltage Operation in Modern DRAM Devices
inferredcites →https://doi.org/10.1145/3123939.3123945openalex-snapshot
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
inferredcites →https://doi.org/10.1145/3162616openalex-snapshot
Characterizing 3D Floating Gate NAND Flash
inferredcites →https://doi.org/10.1145/3219617.3219661openalex-snapshot
What Your DRAM Power Models Are Not Telling You
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A case for redundant arrays of inexpensive disks (RAID)
inferredcites →https://doi.org/10.1184/r1/6724127.v1openalex-snapshot
Understanding and Improving the Latency of DRAM-Based Memory Systems
inferredcites →https://doi.org/10.23919/date.2017.7927156openalex-snapshot
The RowHammer problem and other issues we may face as memory becomes denser
inferredcites →https://doi.org/10.23919/date.2018.8342023openalex-snapshot
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
inferredcites →https://doi.org/10.25080/majora-92bf1922-011openalex-snapshot
Statsmodels: Econometric and Statistical Modeling with Python
inferredcites →https://doi.org/10.48550/arxiv.1711.11427openalex-snapshot
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
inferredcites →https://doi.org/10.5555/1960475.1960493openalex-snapshot
Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
inferredcites →https://doi.org/10.5555/2591305.2591311openalex-snapshot
Wear unleveling: improving NAND flash lifetime by balancing page endurance
inferredcites →https://doi.org/10.5555/2591305.2591312openalex-snapshot
Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling
inferredcites →https://doi.org/10.5555/2750482.2750500openalex-snapshot
How much can data compressibility help to improve NAND flash memory lifetime
inferredcites →https://doi.org/10.7873/date.2013.266openalex-snapshot
Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling
inferredcites →https://doi.org/10.7873/date2014.186openalex-snapshot
Exploiting expendable process-margins in DRAMs for run-time performance optimization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Large‐Scale and Highly Reliable Hopfield Neural Networks Using Vertical NAND Flash Memory for the In‐Memory Associative Computing
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Channel width-dependent Schottky barrier modulation in ambipolar charge-trap memory
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3D-MANN: A 3D NAND flash-based reconfigurable architecture for Memory Augmented Neural Networks
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A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy
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Delay-based I/O request scheduling in SSDs
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Adaptive weight-bit inversion for state error reduction for robust and efficient deep neural network inference using MLC NAND Flash
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DeferRefresh: Deferred retention-aware refresh for archival management on high-density SSD-based RAID systems
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DNN‐aided read‐voltage threshold optimization for MLC flash memory with finite block length
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Interface engineering of 9X stacked 3D NAND flash memory using hydrogen post-treatment annealing
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An Early-Life NAND Flash Endurance Prediction System
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Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
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Intelligent Read Framework With Meta-Learning for NAND Flash Memory Under Process Variation
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FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
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SuperCopyback: Revisiting Copyback on Modern High-Performance NAND Flash-based SSDs
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LUT-Optimized Decoding of QC-LDPC Codes for Flash Memory with EoL Layers Variation Model
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MGC: Multiple-Gray-Code for 3D NAND Flash based High-Density SSDs
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Target Reprogramming for Tightening Threshold Voltage Distribution in Charge Trapping 3D NAND Flash Memory
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BABOL: A Software-Defined NAND Flash Controller
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How the common retention acceleration method of 3D NAND flash memory goes wrong?
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Proactive Stripe Reconstruction to Improve Cache Use Efficiency of SSD-Based RAID Systems
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Achieving Near-Zero Read Retry for 3D NAND Flash Memory
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A Low-Error-Tolerance Coding Strategy for TLC NAND Flash Memory
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Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement
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FairyWREN: A Sustainable Cache for Emerging Write-Read-Erase Flash Interfaces
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A Context-Aware Huffman Coding for Resource-Constrained Systems using NAND Flash Memory
inferred← citeshttps://doi.org/10.1145/3796534openalex-snapshot
DyLDPC: A Dynamic LDPC Code with Variable Correction Capability to Improve Decoding Performance for 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.1186/s13638-025-02506-4openalex-snapshot
Enhancing reliability of 3D portable SSDs by storing redundant data to RRAM cache considering layer-to-layer process variation
inferred← citeshttps://doi.org/10.1360/ssi-2021-0150openalex-snapshot
LDPC code-dependent quantization for the NAND flash channel
inferred← citeshttps://doi.org/10.15622/ia.22.2.4openalex-snapshot
Performance Analysis of Concatenated Coding to Increase the Endurance of Multilevel NAND Flash Memory
inferred← citeshttps://doi.org/10.1587/elex.18.20210103openalex-snapshot
Error source and latency-aware read performance optimization scheme for aged SSDs
inferred← citeshttps://doi.org/10.2139/ssrn.5339569openalex-snapshot
A Novel Cu Filling Method for High-Aspect-Ratio (Ar) Nano-Scale Tsvs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474073openalex-snapshot
Intelligent Architectures for Intelligent Computing Systems
inferred← citeshttps://doi.org/10.3390/e25070965openalex-snapshot
Channel Modeling and Quantization Design for 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.3390/electronics11030424openalex-snapshot
EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage
inferred← citeshttps://doi.org/10.3390/electronics11172738openalex-snapshot
Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory
inferred← citeshttps://doi.org/10.3390/electronics14040738openalex-snapshot
REO: Revisiting Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs
inferred← citeshttps://doi.org/10.3390/eng5010027openalex-snapshot
Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory
inferred← citeshttps://doi.org/10.3390/mi15121447openalex-snapshot
Balancing Page Endurance Variation Between Layers to Extend 3D NAND Flash Memory Lifetime
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