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Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

https://doi.org/10.29007/x3tx
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-36400-5_14openalex-snapshot
An Optimized S-Box Circuit Architecture for Low Power AES Design
inferredcites →https://doi.org/10.1007/3-540-44499-8_9openalex-snapshot
A Comparative Study of Performance of AES Final Candidates Using FPGAs
inferredcites →https://doi.org/10.1007/978-3-319-01857-7openalex-snapshot
Advances in Systems Science : Proceedings of the International Conference on Systems Science 2016 (ICSS 2016)
inferredcites →https://doi.org/10.1007/978-3-642-04101-3openalex-snapshot
Understanding Cryptography: A Textbook For Students And Practitioners
inferredcites →https://doi.org/10.1109/dsd.2006.40openalex-snapshot
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
inferredcites →https://doi.org/10.1109/fccm.2008.42openalex-snapshot
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
inferredcites →https://doi.org/10.1109/iccd.2002.1106754openalex-snapshot
A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
inferredcites →https://doi.org/10.1109/jssc.2002.808300openalex-snapshot
Design and performance testing of a 2.29-GB/s rijndael processor
inferredcites →https://doi.org/10.1109/mdt.2009.81openalex-snapshot
Hardware Coprocessor Synthesis from an ANSI C Specification
inferredcites →https://doi.org/10.1109/mwscas.2017.8052985openalex-snapshot
High level synthesis using vivado HLS for optimizations of SHA-3
inferredcites →https://doi.org/10.1109/mwscas.2018.8623880openalex-snapshot
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol
inferredcites →https://doi.org/10.1109/sbesc.2013.36openalex-snapshot
An Implementation of the AES Cipher Using HLS
inferredcites →https://doi.org/10.1109/tvlsi.2004.830936openalex-snapshot
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture
inferredcites →https://doi.org/10.6028/nist.fips.197openalex-snapshot
Advanced Encryption Standard (AES)

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/spy2.254openalex-snapshot
Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey
inferred← citeshttps://doi.org/10.1002/spy2.292openalex-snapshot
Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair
inferred← citeshttps://doi.org/10.1007/s00521-021-06085-5openalex-snapshot
Hybrid semantic deep learning architecture and optimal advanced encryption standard key management scheme for secure cloud storage and intrusion detection
inferred← citeshttps://doi.org/10.1063/5.0256836openalex-snapshot
A review on hybrid methods using playfair and RSA techniques
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00064openalex-snapshot
5G Security: FPGA Implementation of SNOW-V Stream Cipher
inferred← citeshttps://doi.org/10.1109/ginotech63460.2025.11076660openalex-snapshot
Enhancing WSN Performance with a Hybrid Key Management Protocol Using Multitask Deep Learning in IoT Cloud Environments
inferred← citeshttps://doi.org/10.1109/hpec67600.2025.11196518openalex-snapshot
Fast FPGA-Based Implementation of the QP-Dyn Stream Cipher using High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00049openalex-snapshot
Pipelined FPGA Implementation of the QP-DYN Cipher with Scalable Dynamical System Parallelism
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00061openalex-snapshot
Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/pkia67529.2025.11347296openalex-snapshot
An HLS-driven Architectural Design for the PRESENT Lightweight Block Cipher
inferred← citeshttps://doi.org/10.1109/socc56010.2022.9908078openalex-snapshot
Energy-Efficient Black Hole Router Detection in Network-on-Chip
inferred← citeshttps://doi.org/10.11591/ijece.v11i5.pp4221-4232openalex-snapshot
High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications
inferred← citeshttps://doi.org/10.18122/td/1687/boisestateopenalex-snapshot
Secure Network-on-Chip Against Black Hole and Tampering Attacks
inferred← citeshttps://doi.org/10.29007/1j1popenalex-snapshot
Performance Study of Software-based Encrypting Data at Rest
inferred← citeshttps://doi.org/10.29007/lr5zopenalex-snapshot
Peer-to-Peer Data Transfer Evaluation in SmartSSD-based Multi-devices System
inferred← citeshttps://doi.org/10.31891/2307-5732-2022-311-4openalex-snapshot
inferred← citeshttps://doi.org/10.31891/2307-5732-2022-311-4-191-197openalex-snapshot
THE METHOD OF INCREASING THE EFFICIENCY OF SYMMETRICAL BLOCK ENCRYPTION
inferred← citeshttps://doi.org/10.3390/electronics9101665openalex-snapshot
10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform
inferred← citeshttps://doi.org/10.37537/rev.elektron.8.2.201.2024openalex-snapshot
Low Area Implementation of the Advanced Encryption Standard with Counter Mode for System-On-Chip - FPGA
inferred← citeshttps://doi.org/10.5281/zenodo.192064openalex-snapshot
FIGURE 68. C in Immature stages of Calycopis bellera (Hewitson) and C. janeirica (Felder) (Lepidoptera, Lycaenidae, Theclinae, Eumaeini): Taxonomic significance and new evidence for detritivory
inferred← citeshttps://doi.org/10.53759/7669/jmc202303008openalex-snapshot
LM-GA: A Novel IDS with AES and Machine Learning Architecture for Enhanced Cloud Storage Security
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