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Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

https://doi.org/10.3390/electronics10030230

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-319-46493-0_32openalex-snapshot

XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks

inferredcites →https://doi.org/10.1016/j.neucom.2017.09.046openalex-snapshot

FP-BNN: Binarized neural network on FPGA

inferredcites →https://doi.org/10.1109/access.2019.2956508openalex-snapshot

A Survey on the New Generation of Deep Learning in Image Processing

inferredcites →https://doi.org/10.1109/asap.2019.00-43openalex-snapshot

LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism

inferredcites →https://doi.org/10.1109/coolchips.2018.8373076openalex-snapshot

XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks

inferredcites →https://doi.org/10.1109/cvpr.2016.90openalex-snapshot

Deep Residual Learning for Image Recognition

inferredcites →https://doi.org/10.1109/cvprw.2017.48openalex-snapshot

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

inferredcites →https://doi.org/10.1109/dsd51259.2020.00057openalex-snapshot

Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

inferredcites →https://doi.org/10.1109/fccm.2018.00018openalex-snapshot

ReBNet: Residual Binarized Neural Network

inferredcites →https://doi.org/10.1109/fccm.2019.00060openalex-snapshot

SimBNN: A Similarity-Aware Binarized Neural Network Acceleration Framework

inferredcites →https://doi.org/10.1109/fpl.2018.00016openalex-snapshot

FBNA: A Fully Binarized Neural Network Accelerator

inferredcites →https://doi.org/10.1109/fpt.2016.7929192openalex-snapshot

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC

inferredcites →https://doi.org/10.1109/icassp.2017.7953288openalex-snapshot

LogNet: Energy-efficient neural networks using logarithmic computation

inferredcites →https://doi.org/10.1109/ipdpsw.2017.95openalex-snapshot

On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA

inferredcites →https://doi.org/10.1109/iscas.2018.8351807openalex-snapshot

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?

inferredcites →https://doi.org/10.1109/iscas45731.2020.9181099openalex-snapshot

Training Progressively Binarizing Deep Networks using FPGAs

inferredcites →https://doi.org/10.1109/jproc.2017.2761740openalex-snapshot

Efficient Processing of Deep Neural Networks: A Tutorial and Survey

inferredcites →https://doi.org/10.1109/mwscas.2017.8052915openalex-snapshot

Deep learning binary neural network on an FPGA

inferredcites →https://doi.org/10.1109/tc.2020.2978817openalex-snapshot

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

inferredcites →https://doi.org/10.1109/tcad.2018.2857019openalex-snapshot

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

inferredcites →https://doi.org/10.1109/tcsi.2020.3011984openalex-snapshot

A Partially Binarized Hybrid Neural Network System for Low-Power and Resource Constrained Human Activity Recognition

inferredcites →https://doi.org/10.1145/3020078.3021744openalex-snapshot

FINN

inferredcites →https://doi.org/10.1145/3242897openalex-snapshot

FINN- R

inferredcites →https://doi.org/10.23919/date48585.2020.9116220openalex-snapshot

BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

inferredcites →https://doi.org/10.23919/fpl.2017.8056820openalex-snapshot

Accelerating low bit-width convolutional neural networks with embedded FPGA

inferredcites →https://doi.org/10.3390/electronics8030292openalex-snapshot

A State-of-the-Art Survey on Deep Learning Theory and Architectures

inferredcites →https://doi.org/10.3390/electronics8050563openalex-snapshot

VLSI Implementation of Restricted Coulomb Energy Neural Network with Improved Learning Scheme

inferredcites →https://doi.org/10.3390/electronics8060661openalex-snapshot

A Review of Binarized Neural Networks

inferredcites →https://doi.org/10.3390/electronics8121397openalex-snapshot

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

inferredcites →https://doi.org/10.3390/electronics9040555openalex-snapshot

CNN-Based Vehicle Target Recognition with Residual Compensation for Circular SAR Imaging

inferredcites →https://doi.org/10.3929/ethz-b-000329926openalex-snapshot

XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks

inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot

Very Deep Convolutional Networks for Large-Scale Image Recognition

inferredcites →https://doi.org/10.48550/arxiv.1511.00363openalex-snapshot

BinaryConnect: Training Deep Neural Networks with binary weights during propagations

inferredcites →https://doi.org/10.48550/arxiv.1602.02830openalex-snapshot

Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1

inferredcites →https://doi.org/10.48550/arxiv.1605.04711openalex-snapshot

Ternary Weight Networks

inferredcites →https://doi.org/10.48550/arxiv.1606.06160openalex-snapshot

DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients

inferredcites →https://doi.org/10.48550/arxiv.1702.03044openalex-snapshot

Incremental Network Quantization: Towards Lossless CNNs with Low-Precision Weights

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s00521-023-08567-0openalex-snapshot

Spike time displacement-based error backpropagation in convolutional spiking neural networks

inferred← citeshttps://doi.org/10.1016/j.compeleceng.2022.108302openalex-snapshot

Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network

inferred← citeshttps://doi.org/10.1109/access.2023.3258360openalex-snapshot

A Systematic Literature Review on Binary Neural Networks

inferred← citeshttps://doi.org/10.1109/access.2024.3392240openalex-snapshot

FPGA Implementation of a Fault-Tolerant Fused and Branched CNN Accelerator With Reconfigurable Capabilities

inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00022openalex-snapshot

BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC

inferred← citeshttps://doi.org/10.1109/icicdt59917.2023.10332413openalex-snapshot

A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit

inferred← citeshttps://doi.org/10.1109/icriset64803.2025.11252020openalex-snapshot

A Design and Implementation of Power Efficient VLSI Sensor Node Interface with BTC Model and Threshold Optimization

inferred← citeshttps://doi.org/10.1109/incc64392.2024.00018openalex-snapshot

Design of Cost-Effective Binary Neural Network's Accelerator with Ultra-Low Latency

inferred← citeshttps://doi.org/10.1109/isdfs69419.2026.11459016openalex-snapshot

High-Performance Distributed Deep Learning Using Adaptive Parallelism and Dynamic Workload Scheduling

inferred← citeshttps://doi.org/10.1109/tcsi.2025.3611134openalex-snapshot

A High-Energy-Efficiency Lightweight BNN Accelerator for Arrhythmia Detection

inferred← citeshttps://doi.org/10.1109/tcsii.2023.3241154openalex-snapshot

Towards Reconfigurable CNN Accelerator for FPGA Implementation

inferred← citeshttps://doi.org/10.1109/tcsii.2024.3440965openalex-snapshot

BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy With 1.9 Mbit On-Chip Parameters in a 28-nm FPGA

inferred← citeshttps://doi.org/10.1145/3657282openalex-snapshot

Lightweight Deep Learning for Resource-Constrained Environments: A Survey

inferred← citeshttps://doi.org/10.1145/3787109.3815278openalex-snapshot

TLG2LUT6: Threshold Logic Mapping for Sub-Nanosecond Binary Neural Network Inference

inferred← citeshttps://doi.org/10.12792/iciae2022.026openalex-snapshot

Evaluation of the Design Exploration of a Binarized Neural Network for FPGA using HDLRuby

inferred← citeshttps://doi.org/10.2139/ssrn.4883626openalex-snapshot

Enhancing Bnn Storage and Performance Requirements Via Efficient Quantization and Variable Encoding

inferred← citeshttps://doi.org/10.3389/fhpcp.2026.1853655openalex-snapshot

Enhancing BNN storage and performance requirements via efficient quantization and variable encoding

inferred← citeshttps://doi.org/10.3390/chips4020024openalex-snapshot

NeuroAdaptiveNet: A Reconfigurable FPGA-Based Neural Network System with Dynamic Model Selection

inferred← citeshttps://doi.org/10.3390/electronics11060945openalex-snapshot

A Survey on Efficient Convolutional Neural Networks and Hardware Acceleration

inferred← citeshttps://doi.org/10.3390/iot5040041openalex-snapshot

An Optimised CNN Hardware Accelerator Applicable to IoT End Nodes for Disruptive Healthcare

inferred← citeshttps://doi.org/10.3390/s21103407openalex-snapshot

An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated

inferred← citeshttps://doi.org/10.3390/s21113906openalex-snapshot

Command Recognition Using Binarized Convolutional Neural Network with Voice and Radar Sensors for Human-Vehicle Interaction

inferred← citeshttps://doi.org/10.3390/s22010348openalex-snapshot

System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics

inferred← citeshttps://doi.org/10.70675/b7632edfz3807z4b8fzb462z31a6dcf54161openalex-snapshot

Design of mixed system (RRAM memory & digital) targeting binary neural network hardware accelerator

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