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A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

https://doi.org/10.3390/electronics10162023

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/sec.1479openalex-snapshot

Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation

inferredcites →https://doi.org/10.1002/sec.651openalex-snapshot

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

inferredcites →https://doi.org/10.1007/s00145-019-09342-yopenalex-snapshot

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

inferredcites →https://doi.org/10.1007/s10470-015-0599-7openalex-snapshot

High-performance elliptic curve cryptoprocessors over $$\varvec{GF(2^{m})}$$ G F ( 2 m ) on Koblitz curves

inferredcites →https://doi.org/10.1007/s10617-017-9189-5openalex-snapshot

FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals

inferredcites →https://doi.org/10.1007/s10836-016-5598-9openalex-snapshot

A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

inferredcites →https://doi.org/10.1007/s11227-018-2317-6openalex-snapshot

Elliptic Curve Cryptography hardware accelerator for high-performance secure servers

inferredcites →https://doi.org/10.1007/s11277-016-3385-7openalex-snapshot

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

inferredcites →https://doi.org/10.1007/s11277-018-5606-8openalex-snapshot

Compact and High Speed Architectures of KASUMI Block Cipher

inferredcites →https://doi.org/10.1007/s11277-018-6031-8openalex-snapshot

Parallel-Pipelined-Memory-Based Blowfish Design with Reduced FPGA Utilization for Secure ZigBee Real-Time Transmission

inferredcites →https://doi.org/10.1007/s12652-020-02403-2openalex-snapshot

RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications

inferredcites →https://doi.org/10.1007/s13369-017-2925-0openalex-snapshot

AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

inferredcites →https://doi.org/10.1007/s13389-019-00211-9openalex-snapshot

Fast unified elliptic curve point multiplication for NIST prime curves on FPGAs

inferredcites →https://doi.org/10.1016/j.aeue.2020.153383openalex-snapshot

An area-efficient ECC architecture over GF( 2 m ) for resource-constrained applications

inferredcites →https://doi.org/10.1016/j.compeleceng.2013.11.014openalex-snapshot

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

inferredcites →https://doi.org/10.1016/j.jesit.2015.04.002openalex-snapshot

Power efficient and high performance VLSI architecture for AES algorithm

inferredcites →https://doi.org/10.1016/j.jksuci.2016.01.004openalex-snapshot

Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA

inferredcites →https://doi.org/10.1016/j.jksuci.2020.08.005openalex-snapshot

A lightweight AES algorithm implementation for encrypting voice messages using field programmable gate arrays

inferredcites →https://doi.org/10.1016/j.jksues.2018.07.002openalex-snapshot

An efficient AES implementation using FPGA with enhanced security features

inferredcites →https://doi.org/10.1016/j.mejo.2010.04.004openalex-snapshot

An ASIC implementation of low power and high throughput blowfish crypto algorithm

inferredcites →https://doi.org/10.1016/j.mejo.2014.05.004openalex-snapshot

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

inferredcites →https://doi.org/10.1016/j.mejo.2019.05.005openalex-snapshot

FPGA implementation of sound encryption system based on fractional-order chaotic systems

inferredcites →https://doi.org/10.1016/j.micpro.2015.07.005openalex-snapshot

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

inferredcites →https://doi.org/10.1016/j.micpro.2015.11.015openalex-snapshot

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

inferredcites →https://doi.org/10.1016/j.micpro.2015.12.002openalex-snapshot

A high-speed AES design resistant to fault injection attacks

inferredcites →https://doi.org/10.1016/j.micpro.2019.102972openalex-snapshot

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

inferredcites →https://doi.org/10.1049/iet-cds.2018.5273openalex-snapshot

Hardware architectures for PRESENT block cipher and their FPGA implementations

inferredcites →https://doi.org/10.1049/iet-cds.2018.5354openalex-snapshot

8‐bit serialised architecture of SEED block cipher for constrained devices

inferredcites →https://doi.org/10.1049/iet-cdt.2018.5098openalex-snapshot

Low‐complexity and differential power analysis (DPA)‐resistant two‐folded power‐aware Rivest–Shamir–Adleman (RSA) security schema implementation for IoT‐connected devices

inferredcites →https://doi.org/10.1049/iet-cdt.2019.0157openalex-snapshot

Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

inferredcites →https://doi.org/10.1049/iet-cdt.2019.0179openalex-snapshot

High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications

inferredcites →https://doi.org/10.1080/00051144.2020.1816388openalex-snapshot

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

inferredcites →https://doi.org/10.1109/sas.2015.7133616openalex-snapshot

Smart meters as part of a sensor network for monitoring the low voltage grid

inferredcites →https://doi.org/10.1109/tcad.2017.2740286openalex-snapshot

Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA

inferredcites →https://doi.org/10.1109/tcsi.2017.2686783openalex-snapshot

Lightweight Hardware Architectures for the Present Cipher in FPGA

inferredcites →https://doi.org/10.1109/tie.2020.3001850openalex-snapshot

Model-Based Stealth Attack to Networked Control System Based on Real-Time Ethernet

inferredcites →https://doi.org/10.1109/tvlsi.2020.3033928openalex-snapshot

Area-Efficient Nano-AES Implementation for Internet-of-Things Devices

inferredcites →https://doi.org/10.1142/s0218126619500622openalex-snapshot

Low-Cost AES-128 Implementation for Edge Devices in IoT Applications

inferredcites →https://doi.org/10.1155/2017/8051728openalex-snapshot

Stealthy Hardware Trojan Based Algebraic Fault Analysis of HIGHT Block Cipher

inferredcites →https://doi.org/10.11591/ijece.v6i1.8388openalex-snapshot

High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

inferredcites →https://doi.org/10.11591/ijeecs.v18.i2.pp774-781openalex-snapshot

DES encryption and decryption algorithm implementation based on FPGA

inferredcites →https://doi.org/10.13154/tches.v2018.i3.596-626openalex-snapshot

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

inferredcites →https://doi.org/10.14257/ijseia.2016.10.6.07openalex-snapshot

FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology

inferredcites →https://doi.org/10.2478/s13537-013-0112-2openalex-snapshot

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

inferredcites →https://doi.org/10.3390/electronics9101665openalex-snapshot

10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

inferredcites →https://doi.org/10.3390/en14051277openalex-snapshot

Massive Generation of Customer Load Profiles for Large Scale State Estimation Deployment: An Approach to Exploit AMI Limited Data

inferredcites →https://doi.org/10.3390/s19040913openalex-snapshot

FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher

inferredcites →https://doi.org/10.4236/cs.2016.74032openalex-snapshot

Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

inferredcites →https://doi.org/10.4236/cs.2017.89016openalex-snapshot

A Fast FPGA Implementation for Triple DES Encryption Scheme

inferredcites →https://doi.org/10.46586/tches.v2018.i3.596-626openalex-snapshot

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

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inferred← citeshttps://doi.org/10.32985/ijeces.14.1.7openalex-snapshot

Tuna Swarm Optimization with 3D-chaotic map and DNA encoding for image encryption with lossless image compression based on FPGA

inferred← citeshttps://doi.org/10.3390/app13127085openalex-snapshot

Utilizing Trusted Lightweight Ciphers to Support Electronic-Commerce Transaction Cryptography

inferred← citeshttps://doi.org/10.3390/cryptography9040078openalex-snapshot

Flexible and Area-Efficient Codesign Implementation of AES on FPGA

inferred← citeshttps://doi.org/10.3390/electronics15153306openalex-snapshot

Side-Channel Leakage Assessment of an FPGA-Based AES-256 Implementation Using TVLA

inferred← citeshttps://doi.org/10.3390/jcp6010001openalex-snapshot

Huffman Tree and Binary Conversion for Efficient and Secure Data Encryption and Decryption

inferred← citeshttps://doi.org/10.3390/s21248347openalex-snapshot

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

inferred← citeshttps://doi.org/10.3390/s22114269openalex-snapshot

IoT-Based Multi-Sensor Healthcare Architectures and a Lightweight-Based Privacy Scheme

inferred← citeshttps://doi.org/10.3390/s25195936openalex-snapshot

The Untapped Potential of Ascon Hash Functions: Benchmarking, Hardware Profiling, and Application Insights for Secure IoT and Blockchain Systems

inferred← citeshttps://doi.org/10.37396/jsc.v6i2.326openalex-snapshot

Sistem Keamanan Kartu NFC Menggunakan Metode AES pada Sistem Pembayaran Elektronik

inferred← citeshttps://doi.org/10.4236/me.2023.149062openalex-snapshot

Review of Algorithms for Securing Data Transmission in Mobile Banking

inferred← citeshttps://doi.org/10.48084/etasr.9852openalex-snapshot

Innovative Fault Detection for AES in Embedded Systems: Advancing Resilient and Sustainable Digital Security

inferred← citeshttps://doi.org/10.52465/joscex.v4i4.274openalex-snapshot

A text security evaluation based on advanced encryption standard algorithm

inferred← citeshttps://doi.org/10.56919/usci.2223.007openalex-snapshot

Resource Limitations for Wireless Sensor Networks to Establish a Comprehensive Security System in the 5G Network

inferred← citeshttps://doi.org/10.56919/usci.2322.007openalex-snapshot

Resource Limitations for Wireless Sensor Networks to Establish a Comprehensive Security System in the 5G Network

inferred← citeshttps://doi.org/10.7717/peerj-cs.3833openalex-snapshot

Design and field programmable gate array implementation of a Rossler-driven four-dimensional hyperchaotic Rossler–advanced encryption standard framework for image encryption

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