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High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

https://doi.org/10.3390/electronics11244202

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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A new design technique for column compression multipliers

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A fast parallel multiplier-accumulator using the modified Booth algorithm

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4-bit Wallace and Dadda Multiplier design using novel hybrid 3-2 Counter

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Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs

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Design of an algorithmic Wallace multiplier using high speed counters

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Area efficient modified vedic multiplier

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Low power wallace tree multiplier using modified full adder

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Performance analysis for Vedic multiplier using modified full adders

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Design and implementation of 32-bit adders using various full adders

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Multiplier structures for low power applications in deep-CMOS

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Design and Implementation of an Efficient Dadda Multiplier Using Novel Compressors and Fast Adder

inferredcites →https://doi.org/10.1109/pervasive.2015.7087207openalex-snapshot

Design of area and power aware reduced Complexity Wallace Tree multiplier

inferredcites →https://doi.org/10.1109/pgec.1964.263830openalex-snapshot

A Suggestion for a Fast Multiplier

inferredcites →https://doi.org/10.1109/rteict.2016.7808163openalex-snapshot

Design of delay efficient modified 16 bit Wallace multiplier

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Fast Multipliers

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A Reduced Complexity Wallace Multiplier Reduction

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Design and Analysis of Approximate Compressors for Multiplication

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RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

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An Efficient Dadda Multiplier using Approximate Adder

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Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

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Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

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Trading Accuracy for Power with an Underdesigned Multiplier Architecture

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A comparison of Dadda and Wallace multiplier delays

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Low-Area Wallace Multiplier

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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FPGA ‐Based Design of Ultra‐Efficient Approximate Adders for High‐Fidelity Image Processing: A Logic‐Optimized Approach

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Multi-Threshold 2:1-Multiplexer-Based Novel UT-Vedic 4 × 4-Bit Multiplier

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Delay Assessment of Parallel Multiplier Using Ultra-Scale FPGA Devices

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High Performance MAC Unit Design with Grouping and Decomposition Multiplier and 18 T Gate Diffusion Input-Transmission Gate Adder

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Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding

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A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers

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IoT-driven optimization of a NxN enhanced pipeline multiplier

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Design and synthesis of reversible Vedic multiplier using cadence 180 nm technology for low-power high-speed applications

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A scalable automated framework for multiply-accumulate unit design in high-performance computing applications

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Implementation of N x N Enhanced Multiplier Using Reversible Logic Gate

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Very-Large-Scale Integration (VLSI) Implementation and Performance Comparison of Multiplier Topologies for Fixed- and Floating-Point Numbers

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A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending

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