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Using transformations and verification in circuit design

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/10817.1573-0670openalex-snapshot

Journal of Automated Reasoning

inferredcites →https://doi.org/10.1007/3-540-15976-2_12openalex-snapshot

A procedure for automatically proving the termination of a set of rewrite rules

inferredcites →https://doi.org/10.1007/3-540-16780-3_142openalex-snapshot

REVE a rewrite rule laboratory

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot

VLSI Specification, Verification and Synthesis

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot

HOL: A Proof Generating System for Higher-Order Logic

inferredcites →https://doi.org/10.1007/978-3-642-95432-0_7openalex-snapshot

Optimizing Synchronous Circuitry by Retiming (Preliminary Version)

inferredcites →https://doi.org/10.1007/978-94-011-1793-7_16openalex-snapshot

The Notion of Proof in Hardware Verification

inferredcites →https://doi.org/10.1007/bf00243000openalex-snapshot

The notion of proof in hardware verification

inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot

Microprocessor design verification

inferredcites →https://doi.org/10.1007/bf01759032openalex-snapshot

Retiming synchronous circuitry

inferredcites →https://doi.org/10.1016/0167-9260(89)90004-7openalex-snapshot

Formal specification and verification of microprocessor systems

inferredcites →https://doi.org/10.1016/0378-4754(89)90181-xopenalex-snapshot

A computational logic handbook

inferredcites →https://doi.org/10.1016/c2013-0-10412-6openalex-snapshot

A Computational Logic Handbook

inferredcites →https://doi.org/10.1109/32.58789openalex-snapshot

Debugging Larch shared language specifications

inferredcites →https://doi.org/10.1109/sfcs.1981.34openalex-snapshot

Optimizing synchronous systems

inferredcites →https://doi.org/10.1201/9781420049671.ch61openalex-snapshot

Microprocessor Design Verification

inferredcites →https://doi.org/10.7146/dpb.v17i258.7842openalex-snapshot

Verification of VLSI Circuits Using LP

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Combining Stream-Based and State-Based Verification Techniques

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Elementary Microarchitecture Algebra

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PVS: A prototype verification system

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An overview of Larch

inferred← citeshttps://doi.org/10.1007/3-540-56922-7_25openalex-snapshot

Computer-assisted simulation proofs

inferred← citeshttps://doi.org/10.1007/3-540-58179-0_44openalex-snapshot

Automatic verification of pipelined microprocessor control

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Ground temporal logic: A logic for hardware verification

inferred← citeshttps://doi.org/10.1007/3-540-59047-1_40openalex-snapshot

Reasoning about pipelines with structural hazards

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Effective theorem proving for hardware verification

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Formal verification of characteristic properties

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Distributed larch prover (DLP): An experiment in parallelizing a rewrite-rule based prover

inferred← citeshttps://doi.org/10.1007/978-1-4612-2704-5openalex-snapshot

Larch: Languages and Tools for Formal Specification

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A Formal System for Correct Hardware Design

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Proving the Correctness of Processors with Delayed Branch Using Delayed PC

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Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods

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Gordon's computer: A hardware verification case study in OBJ3

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A practical method for rigorously controllable hardware design

inferred← citeshttps://doi.org/10.1007/bfb0031806openalex-snapshot

Self-consistency checking

inferred← citeshttps://doi.org/10.1007/bfb0031817openalex-snapshot

Formal synthesis in circuit design — A classification and survey

inferred← citeshttps://doi.org/10.1007/bfb0031821openalex-snapshot

Mechanically checking a lemma used in an automatic verification tool

inferred← citeshttps://doi.org/10.1007/bfb0031822openalex-snapshot

Automatic generation of invariants in processor verification

inferred← citeshttps://doi.org/10.1007/bfb0105401openalex-snapshot

Coq and hardware verification: A case study

inferred← citeshttps://doi.org/10.1016/b978-044482106-5/50027-2openalex-snapshot

Design by Transformation of Synchronous Descriptions

inferred← citeshttps://doi.org/10.1109/32.663997openalex-snapshot

Formal verification of concurrent programs using the Larch prover

inferred← citeshttps://doi.org/10.1109/aspdac.1995.486362openalex-snapshot

Verifying pipelined microprocessors

inferred← citeshttps://doi.org/10.1109/hpdc.1996.546185openalex-snapshot

Parallel user interfaces for parallel applications

inferred← citeshttps://doi.org/10.1109/icfem.1997.630421openalex-snapshot

Systematic formal verification of interpreters

inferred← citeshttps://doi.org/10.1109/reldis.1994.336902openalex-snapshot

Interaction of formal design systems in the development of a fault-tolerant clock synchronization circuit

inferred← citeshttps://doi.org/10.1109/tc.2007.1073openalex-snapshot

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot

Integrating Formal Verification into an Advanced Computer Architecture Course

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Formal verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods

inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot

Formal verification in hardware design

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Integrating Formal Verification Into An Advanced Computer Architecture Course

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Analog Control of Continuous Copper Wire Annealing Based on Temperature Detecting

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