On the public citation graph

Retargeting a hardware compiler using protocol converters

https://doi.org/10.1007/bf01214557
0 signed · 26 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4471-3544-9_7openalex-snapshot
Towards Truly Delay-Insensitive Circuit Realizations of Process Algebras
inferredcites →https://doi.org/10.1007/bf01178564openalex-snapshot
Receptive process theory
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1016/0020-0190(85)90078-xopenalex-snapshot
The probe: An addition to communication primitives
inferredcites →https://doi.org/10.1016/0141-9331(92)90081-4openalex-snapshot
VLSI asynchronous systems: specification and synthesis
inferredcites →https://doi.org/10.1017/cbo9780511585777openalex-snapshot
Handshake Circuits
inferredcites →https://doi.org/10.1049/ir:19930076openalex-snapshot
Breaking step the return of asynchronous logic
inferredcites →https://doi.org/10.1109/iccd.1988.25680openalex-snapshot
VLSI programming and silicon compilation-a novel approach from Philips research
inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot
Micropipelines
inferredcites →https://doi.org/10.21236/ada443297openalex-snapshot
Synthesis of Self-Timed Circuits by Program Transformation
inferredcites →https://doi.org/10.21236/ada444293openalex-snapshot
A Synthesis Method for Self-Timed VLSI Circuits
inferredcites →https://doi.org/10.21236/ada447033openalex-snapshot
Syntax-Directed Translation of Concurrent Programs into Self-Timed Circuits
inferredcites →https://doi.org/10.7551/mitpress/1102.003.0005openalex-snapshot
Syntax-directed Translation of Concurrent Programs into Self-timed Circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
inferredcites →https://doi.org/10.7907/j438-dz84openalex-snapshot
Automated Compilation of Concurrent Programs into Self-Timed Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44798-9_29openalex-snapshot
Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip
inferred← citeshttps://doi.org/10.1007/3-540-63465-7_214openalex-snapshot
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research
inferred← citeshttps://doi.org/10.1007/bf00936948openalex-snapshot
Constructing hardware-software systems from a single description
inferred← citeshttps://doi.org/10.1007/bf01211459openalex-snapshot
Verified compilation of communicating processes into clocked circuits
inferred← citeshttps://doi.org/10.1007/s10009-002-0096-zopenalex-snapshot
Refinement-based formal verification with heterogeneous timing
inferred← citeshttps://doi.org/10.1109/43.573835openalex-snapshot
Synchronous emulation of asynchronous circuits
inferred← citeshttps://doi.org/10.1109/apaqs.2001.990012openalex-snapshot
Constructing hardware/software interface using protocol converters
inferred← citeshttps://doi.org/10.1109/async.2004.1299293openalex-snapshot
Bolstering faith in GasP circuits through formal verification
inferred← citeshttps://doi.org/10.1109/tcad.2005.858349openalex-snapshot
Semihiding operators and active-edge specification
inferred← citeshttps://doi.org/10.14236/ewic/dcc1996.3openalex-snapshot
Deriving Two-Phase Modules for a Multi-Target Hardware Compiler
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