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Scheduling a system of nonsingular affine recurrence equations onto a processor array

https://doi.org/10.1007/bf02477177
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bfb0040399openalex-snapshot
Converting affine recurrence equations to quasi-uniform recurrence equations
inferredcites →https://doi.org/10.1016/0743-7315(85)90029-2openalex-snapshot
Parallelism detection and transformation techniques useful for VLSI algorithms
inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot
Regular iterative algorithms and their implementation on processor arrays
inferredcites →https://doi.org/10.1109/arrays.1988.18079openalex-snapshot
Time optimal linear schedules for algorithms with uniform dependencies
inferredcites →https://doi.org/10.1109/arrays.1988.18080openalex-snapshot
Broadcast removal in systolic algorithms
inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot
VLSI Array processors
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/sfcs.1981.34openalex-snapshot
Optimizing synchronous systems
inferredcites →https://doi.org/10.1109/tassp.1984.1164450openalex-snapshot
Combinatorial optimization:Algorithms and complexity
inferredcites →https://doi.org/10.1109/tc.1982.1675929openalex-snapshot
On the Analysis and Synthesis of VLSI Algorithms
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676744openalex-snapshot
Mapping Homogeneous Graphs on Linear Arrays
inferredcites →https://doi.org/10.1117/12.944011openalex-snapshot
Selecting Systolic Designs Using Linear Transformations Of Space-Time
inferredcites →https://doi.org/10.1137/0114108openalex-snapshot
Properties of a Model for Parallel Computations: Determinacy, Termination, Queueing
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.1145/800015.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
inferredcites →https://doi.org/10.2307/2322374openalex-snapshot
Combinatorial Optimization: Algorithms and Complexity.
inferredcites →https://doi.org/10.56021/9781421407944openalex-snapshot
Matrix Computations

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4615-3242-2_6openalex-snapshot
Regular Array Synthesis for Image and Video Applications
inferred← citeshttps://doi.org/10.1007/bf02106104openalex-snapshot
Mapping 3-D IIR digital filter onto systolic arrays
inferred← citeshttps://doi.org/10.1016/0024-3795(92)90345-bopenalex-snapshot
Decoupling the dimension of a system of affine recurrence equations
inferred← citeshttps://doi.org/10.1016/0167-9260(93)90012-2openalex-snapshot
An improved systolic algorithm for the algebraic path problem
inferred← citeshttps://doi.org/10.1016/s0747-7171(06)80005-2openalex-snapshot
Synthesis aspects in the design of efficient processor arrays from affine recurrence equations
inferred← citeshttps://doi.org/10.1080/01495730008947354openalex-snapshot
A LIBRARY FOR DOING POLYHEDRAL OPERATIONS
inferred← citeshttps://doi.org/10.1109/12.589218openalex-snapshot
Multirate VLSI arrays and their synthesis
inferred← citeshttps://doi.org/10.1109/asap.1990.145452openalex-snapshot
Extensions to linear mapping for regular arrays with complex processing elements
inferred← citeshttps://doi.org/10.1109/asap.1991.238894openalex-snapshot
The systematic design of a motion estimation array architecture
inferred← citeshttps://doi.org/10.1109/asap.1995.523640openalex-snapshot
Synthesis of multirate VLSI arrays
inferred← citeshttps://doi.org/10.1109/hicss.1993.270750openalex-snapshot
On the projections of affine recurrence equations
inferred← citeshttps://doi.org/10.1109/mwscas.1989.101866openalex-snapshot
User interface issues in CAD tools for systolic array design
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641063openalex-snapshot
The Exploitation Of Global Operations In Affine Space-time Mapping
inferred← citeshttps://doi.org/10.1109/vlsisp.1992.641069openalex-snapshot
Piecewise Linear Schedules For Recurrence Equations
inferred← citeshttps://doi.org/10.1109/vlsisp.1994.574768openalex-snapshot
What is a multirate array?
inferred← citeshttps://doi.org/10.1145/564870.564888openalex-snapshot
Scheduling reductions on realistic machines
inferred← citeshttps://doi.org/10.1201/9781420040579.ch10openalex-snapshot
Dependence Analysis and Parallelizing Transformations
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