On the public citation graph
Converting affine recurrence equations to quasi-uniform recurrence equations
0 signed · 59 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1007/bfb0040399openalex-snapshot
Converting affine recurrence equations to quasi-uniform recurrence equations
inferredcites →https://doi.org/10.1016/0010-4485(85)90134-4openalex-snapshot
Computational aspects of VLSI
inferredcites →https://doi.org/10.1016/0020-0190(83)90055-8openalex-snapshot
Folding of the plane and the design of systolic arrays
inferredcites →https://doi.org/10.1016/0024-3795(86)90163-1openalex-snapshot
Parallel solution of symmetric positive definite systems with hyperbolic rotations
inferredcites →https://doi.org/10.1016/0041-5553(64)90132-6openalex-snapshot
Representation theory of finite groups and associative algebras
inferredcites →https://doi.org/10.1016/0743-7315(85)90029-2openalex-snapshot
Parallelism detection and transformation techniques useful for VLSI algorithms
inferredcites →https://doi.org/10.1109/5.4402openalex-snapshot
Regular iterative algorithms and their implementation on processor arrays
inferredcites →https://doi.org/10.1109/icassp.1985.1168513openalex-snapshot
Systematic approaches to the design of algorithmically specified systolic arrays
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/proc.1984.12944openalex-snapshot
On supercomputing with systolic/wavefront array processors
inferredcites →https://doi.org/10.1109/tassp.1983.1164051openalex-snapshot
A highly concurrent algorithm and pipeleined architecture for solving Toeplitz systems
inferredcites →https://doi.org/10.1109/tc.1979.1675434openalex-snapshot
Time and Parallel Processor Bounds for Fortran-Like Loops
inferredcites →https://doi.org/10.1109/tc.1982.1675929openalex-snapshot
On the Analysis and Synthesis of VLSI Algorithms
inferredcites →https://doi.org/10.1109/tc.1986.1676652openalex-snapshot
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
inferredcites →https://doi.org/10.1117/12.944011openalex-snapshot
Selecting Systolic Designs Using Linear Transformations Of Space-Time
inferredcites →https://doi.org/10.1137/0114108openalex-snapshot
Properties of a Model for Parallel Computations: Determinacy, Termination, Queueing
inferredcites →https://doi.org/10.1137/0213034openalex-snapshot
A Mathematical Model for the Verification of Systolic Networks
inferredcites →https://doi.org/10.1145/321406.321418openalex-snapshot
The Organization of Computations for Uniform Recurrence Equations
inferredcites →https://doi.org/10.1145/773453.808184openalex-snapshot
Automatic synthesis of systolic arrays from uniform recurrent equations
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4615-3996-4_6openalex-snapshot
Affine Permutations of Matrices on Mesh-Connected Arrays
inferred← citeshttps://doi.org/10.1007/bf00924526openalex-snapshot
Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays
inferred← citeshttps://doi.org/10.1007/bf01192158openalex-snapshot
Geometrical tools to map systems of affine recurrence equations on regular arrays
inferred← citeshttps://doi.org/10.1007/bf01558666openalex-snapshot
Synthesizing systolic arrays with control signals from recurrence equations
inferred← citeshttps://doi.org/10.1007/bf02477177openalex-snapshot
Scheduling a system of nonsingular affine recurrence equations onto a processor array
inferred← citeshttps://doi.org/10.1007/s11265-007-0108-zopenalex-snapshot
Systolic Algorithms and Architectures for High-Throughput Processing Applications
inferred← citeshttps://doi.org/10.1016/0024-3795(92)90345-bopenalex-snapshot
Decoupling the dimension of a system of affine recurrence equations
inferred← citeshttps://doi.org/10.1016/0167-9260(96)00003-xopenalex-snapshot
An integral matrix-based technique for systematic systolic design
inferred← citeshttps://doi.org/10.1016/0743-7315(92)90111-yopenalex-snapshot
Transformation of broadcasts into propagations in systolic algorithms
inferred← citeshttps://doi.org/10.1016/s0010-4655(01)00232-6openalex-snapshot
On loop transformations of nested loops with affine dependencies
inferred← citeshttps://doi.org/10.1016/s0010-4655(01)00234-xopenalex-snapshot
Automatic implementation of affine iterative algorithms: Design flow and communication synthesis
inferred← citeshttps://doi.org/10.1016/s0747-7171(06)80005-2openalex-snapshot
Synthesis aspects in the design of efficient processor arrays from affine recurrence equations
inferred← citeshttps://doi.org/10.1023/a:1008139706909openalex-snapshot
Finding Quadratic Schedules for Affine Recurrence Equations Via Nonsmooth Optimization
inferred← citeshttps://doi.org/10.1080/00207169508804384openalex-snapshot
Procedures for folding transformations
inferred← citeshttps://doi.org/10.1080/00207169608804471openalex-snapshot
Folding transformations for processor arrays
inferred← citeshttps://doi.org/10.1080/00207169708804598openalex-snapshot
Algorithm transformations for computational and data broadcast
inferred← citeshttps://doi.org/10.1109/12.508321openalex-snapshot
On uniformization of affine dependence algorithms
inferred← citeshttps://doi.org/10.1109/12.589218openalex-snapshot
Multirate VLSI arrays and their synthesis
inferred← citeshttps://doi.org/10.1109/2.55468openalex-snapshot
Matrix computations on systolic-type meshes: an introduction to the multimesh graph method
inferred← citeshttps://doi.org/10.1109/78.476445openalex-snapshot
A linear systolic array for recursive least squares
inferred← citeshttps://doi.org/10.1109/78.575701openalex-snapshot
Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures
inferred← citeshttps://doi.org/10.1109/arrays.1988.18077openalex-snapshot
Scheduling a system of affine recurrence equations onto a systolic array
inferred← citeshttps://doi.org/10.1109/asap.1993.397161openalex-snapshot
Multi-rate transformation of directional affine recurrence equations
inferred← citeshttps://doi.org/10.1109/asap.1995.523640openalex-snapshot
Synthesis of multirate VLSI arrays
inferred← citeshttps://doi.org/10.1109/asap.1997.606830openalex-snapshot
Libraries of schedule-free operators in Alpha
inferred← citeshttps://doi.org/10.1109/asap.2003.1212827openalex-snapshot
Switched memory architectures - moving beyond systolic arrays
inferred← citeshttps://doi.org/10.1109/icassp.1991.150617openalex-snapshot
A folding transformation for VLSI IIR filter array design
inferred← citeshttps://doi.org/10.1109/icpp.2001.952064openalex-snapshot
Uniformization of affine dependence programs for parallel embedded system design
inferred← citeshttps://doi.org/10.1109/pacrim.1991.160816openalex-snapshot
Systematic derivation of VLSI arrays for digital DSP algorithms
inferred← citeshttps://doi.org/10.1109/spdp.1992.242753openalex-snapshot
On uniformization of affine dependence algorithms
inferred← citeshttps://doi.org/10.1109/vlsisp.1993.404469openalex-snapshot
A unified systolic design technique based on integral matrix theory
inferred← citeshttps://doi.org/10.1142/s0129053394000111openalex-snapshot
BOUNDED BROADCAST IN SYSTOLIC ARRAYS
inferred← citeshttps://doi.org/10.1145/1375657.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/1379023.1375669openalex-snapshot
A domain specific interconnect for reconfigurable computing
inferred← citeshttps://doi.org/10.1201/9781420040579.ch10openalex-snapshot
Dependence Analysis and Parallelizing Transformations
showing the first 35 of 36 · page through all 36
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.