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Efficient instruction scheduling using finite state automata
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01205182openalex-snapshot
The multiflow trace scheduling compiler
inferredcites →https://doi.org/10.1109/micro.1992.697012openalex-snapshot
Code Generation Schema For Modulo Scheduled Loops
inferredcites →https://doi.org/10.1109/micro.1993.282737openalex-snapshot
Employing finite automata for resource scheduling
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/131080.131081openalex-snapshot
Scanning regular languages by dual finite automata
inferredcites →https://doi.org/10.1145/174675.177904openalex-snapshot
Detecting pipeline structural hazards quickly
inferredcites →https://doi.org/10.1145/192724.192745openalex-snapshot
Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution
inferredcites →https://doi.org/10.1145/231379.231386openalex-snapshot
A reduced multipipeline machine description that preserves scheduling constraints
inferredcites →https://doi.org/10.5555/243846.243909openalex-snapshot
Optimization of machine descriptions for efficient use
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_25openalex-snapshot
Resource Conflict Detection in Simulation of Function Unit Pipelines
inferred← citeshttps://doi.org/10.1016/b978-0-12-815412-0.00018-8openalex-snapshot
Instruction Scheduling
inferred← citeshttps://doi.org/10.1016/j.sysarc.2008.04.002openalex-snapshot
Resource conflict detection in simulation of function unit pipelines
inferred← citeshttps://doi.org/10.1023/a:1018750515365openalex-snapshot
Optimization of Machine Descriptions for Efficient Use
inferred← citeshttps://doi.org/10.1023/a:1020601110391openalex-snapshot
Backtracking-Based Instruction Scheduling to Fill Branch Delay Slots
inferred← citeshttps://doi.org/10.1109/5.964443openalex-snapshot
Instruction scheduling for instruction level parallel processors
inferred← citeshttps://doi.org/10.1109/fccm.2005.39openalex-snapshot
Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip
inferred← citeshttps://doi.org/10.1109/isss.1999.814259openalex-snapshot
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions
inferred← citeshttps://doi.org/10.1109/tvlsi.2003.813011openalex-snapshot
RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions
inferred← citeshttps://doi.org/10.1145/1133255.1134008openalex-snapshot
Automatic instruction scheduler retargeting by reverse-engineering
inferred← citeshttps://doi.org/10.1145/305138.305226openalex-snapshot
Resource usage models for instruction scheduling
inferred← citeshttps://doi.org/10.1145/514191.514208openalex-snapshot
A comparative study of modulo scheduling techniques
inferred← citeshttps://doi.org/10.1145/643470.643475openalex-snapshot
Static resource models for code-size efficient embedded processors
inferred← citeshttps://doi.org/10.18130/v3dr10openalex-snapshot
Pipeline Descriptions for Retargetable Compilers: A Decoupled Approach
inferred← citeshttps://doi.org/10.5555/243846.243909openalex-snapshot
Optimization of machine descriptions for efficient use
inferred← citeshttps://doi.org/10.5555/517554.825772openalex-snapshot
Efficient Backtracking Instruction Schedulers
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