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Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling

https://doi.org/10.1007/bf03356744
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/9781118627372openalex-snapshot
Integer and Combinatorial Optimization
inferredcites →https://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferredcites →https://doi.org/10.1007/bf01205183openalex-snapshot
The cydra 5 minisupercomputer: Architecture and implementation
inferredcites →https://doi.org/10.1007/bf01205184openalex-snapshot
Compiling for the Cydra
inferredcites →https://doi.org/10.1109/92.335014openalex-snapshot
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem
inferredcites →https://doi.org/10.1109/micro.1992.697013openalex-snapshot
Enhanced Modulo Scheduling For Loops With Conditional Branches
inferredcites →https://doi.org/10.1109/micro.1994.717418openalex-snapshot
Minimizing register requirements under resource-constrained rate-optimal software pipelining
inferredcites →https://doi.org/10.1109/micro.1995.476843openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferredcites →https://doi.org/10.1109/micro.1995.476844openalex-snapshot
Hypernode reduction modulo scheduling
inferredcites →https://doi.org/10.1109/superc.1988.44659openalex-snapshot
Squeezing more CPU performance out of a Cray-2 by vector block scheduling
inferredcites →https://doi.org/10.1109/superc.1990.130021openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.1145/1014192.802449openalex-snapshot
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
inferredcites →https://doi.org/10.1145/143095.143141openalex-snapshot
Register allocation for software pipelined loops
inferredcites →https://doi.org/10.1145/143103.143141openalex-snapshot
Register allocation for software pipelined loops
inferredcites →https://doi.org/10.1145/143369.143419openalex-snapshot
Register requirements of pipelined processors
inferredcites →https://doi.org/10.1145/144965.145796openalex-snapshot
Enhanced modulo scheduling for loops with conditional branches
inferredcites →https://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/158511.158519openalex-snapshot
A novel framework of register allocation for software pipelining
inferredcites →https://doi.org/10.1145/173262.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferredcites →https://doi.org/10.1145/192724.192733openalex-snapshot
Minimizing register requirements under resource-constrained rate-optimal software pipelining
inferredcites →https://doi.org/10.1145/224538.224542openalex-snapshot
Optimum modulo schedules for minimum register requirements
inferredcites →https://doi.org/10.1145/2591635.2667171openalex-snapshot
Optimum modulo schedules for minimum register requirements
inferredcites →https://doi.org/10.1145/285930.285973openalex-snapshot
Improving the throughput of a pipeline by insertion of delays
inferredcites →https://doi.org/10.1145/363219.363232openalex-snapshot
An algorithm for finding a fundamental set of cycles of a graph
inferredcites →https://doi.org/10.1145/800110.803575openalex-snapshot
Improving the throughput of a pipeline by insertion of delays
inferredcites →https://doi.org/10.1145/960116.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/989393.989420openalex-snapshot
Software pipelining
inferredcites →https://doi.org/10.1177/109434208900300302openalex-snapshot
The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers
inferredcites →https://doi.org/10.2307/2583737openalex-snapshot
Integer and Combinatorial Optimization
inferredcites →https://doi.org/10.5555/110382.110438openalex-snapshot
Parallelization of loops with exits on pipelined architectures
inferredcites →https://doi.org/10.5555/224659.224940openalex-snapshot
Decomposed software pipelining with reduced register requirement
inferredcites →https://doi.org/10.5555/225160.225210openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferredcites →https://doi.org/10.5555/225160.225211openalex-snapshot
Hypernode reduction modulo scheduling
inferredcites →https://doi.org/10.5555/62972.63004openalex-snapshot
Squeezing more CPU performance out of a Cray-2 by vector block scheduling

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9781118625446.biblioopenalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1007/3-540-36579-6_2openalex-snapshot
Early Control of Register Pressure for Software Pipelined Loops
inferred← citeshttps://doi.org/10.1007/978-1-4757-3337-2_1openalex-snapshot
Equimax: A New Formulation of Optimal Register-Sensitive Scheduling for ILP Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-85097-7_41openalex-snapshot
Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization
inferred← citeshttps://doi.org/10.1007/s00453-001-0103-xopenalex-snapshot
An Experimental Study of Algorithms for Weighted Completion Time Scheduling
inferred← citeshttps://doi.org/10.1007/s10878-010-9332-8openalex-snapshot
SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling
inferred← citeshttps://doi.org/10.1016/j.parco.2008.12.001openalex-snapshot
Periodic register saturation in innermost loops
inferred← citeshttps://doi.org/10.1023/a:1011136427062openalex-snapshot
Design of Processor Arrays for Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1023/a:1019799515784openalex-snapshot
An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors
inferred← citeshttps://doi.org/10.1109/glsv.1998.665328openalex-snapshot
RCRS: a framework for loop scheduling with limited number of registers
inferred← citeshttps://doi.org/10.1109/hsc.2001.924653openalex-snapshot
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
inferred← citeshttps://doi.org/10.1109/hsc.2001.924668openalex-snapshot
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
inferred← citeshttps://doi.org/10.1109/iccad.2001.968606openalex-snapshot
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
inferred← citeshttps://doi.org/10.1109/qest.2004.11openalex-snapshot
Genetic Instruction Scheduling and Register Allocation
inferred← citeshttps://doi.org/10.1109/tc.2007.70752openalex-snapshot
On Periodic Register Need in Software Pipelining
inferred← citeshttps://doi.org/10.1109/tcad.2002.804373openalex-snapshot
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
inferred← citeshttps://doi.org/10.1142/s0129054101000825openalex-snapshot
OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS
inferred← citeshttps://doi.org/10.1142/s012962640400188xopenalex-snapshot
Early Periodic Register Allocation on ILP Processors
inferred← citeshttps://doi.org/10.1145/2180887.2180896openalex-snapshot
Integrated Code Generation for Loops
inferred← citeshttps://doi.org/10.1145/371636.371681openalex-snapshot
RS-FDRA
inferred← citeshttps://doi.org/10.1145/371636.371709openalex-snapshot
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
inferred← citeshttps://doi.org/10.5555/603095.603118openalex-snapshot
CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors
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