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The cydra 5 minisupercomputer: Architecture and implementation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.2247openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/c-m.1981.220595openalex-snapshot
An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
inferredcites →https://doi.org/10.1109/cmpcon.1988.4840openalex-snapshot
Cydra 5 directed dataflow architecture
inferredcites →https://doi.org/10.1109/iccd.1988.25711openalex-snapshot
The Cydra 5 computer system architecture
inferredcites →https://doi.org/10.1109/superc.1990.130118openalex-snapshot
Architecture and implementation of a VLIW supercomputer
inferredcites →https://doi.org/10.1109/tc.1977.5009295openalex-snapshot
Organization of Semiconductor Memories for Parallel-Pipelined Processors
inferredcites →https://doi.org/10.1145/1067649.801721openalex-snapshot
Efficient code generation for horizontal architectures
inferredcites →https://doi.org/10.1145/1067651.801649openalex-snapshot
Very Long Instruction Word architectures and the ELI-512
inferredcites →https://doi.org/10.1145/285930.285985openalex-snapshot
Very long instruction work architectures and the ELI-512
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1177/109434208900300307openalex-snapshot
Appucations Development On the Very Long Instruction Word Cydra-5
inferredcites →https://doi.org/10.5555/110382.110622openalex-snapshot
Architecture and implementation of a VLIW supercomputer
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4615-3200-2_6openalex-snapshot
Compiling for the Cydra 5
inferred← citeshttps://doi.org/10.1007/978-1-4899-7797-7_2openalex-snapshot
Overview of ILP Architectures
inferred← citeshttps://doi.org/10.1007/978-3-540-49051-7_11openalex-snapshot
Efficient State-Diagram Construction Methods for Software Pipelining
inferred← citeshttps://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferred← citeshttps://doi.org/10.1007/bf03356744openalex-snapshot
Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling
inferred← citeshttps://doi.org/10.1016/s0167-8191(97)00095-1openalex-snapshot
Analysis and simulation of an out-of-order execution model in vector multiprocessor systems
inferred← citeshttps://doi.org/10.1023/a:1008842521805openalex-snapshot
Machine-Description Driven Compilers for EPIC and VLIW Processors
inferred← citeshttps://doi.org/10.1109/12.946998openalex-snapshot
Evaluating the use of register queues in software pipelined loops
inferred← citeshttps://doi.org/10.1109/2.820037openalex-snapshot
EPIC: Explicitly Parallel Instruction Computing
inferred← citeshttps://doi.org/10.1109/cgo.2003.1191540openalex-snapshot
Inlining of mathematical functions in HP-UX for Itanium/sup /spl reg// 2
inferred← citeshttps://doi.org/10.1109/hicss.1995.375398openalex-snapshot
An architecture for high instruction level parallelism
inferred← citeshttps://doi.org/10.1109/hpca.1997.569617openalex-snapshot
Architectural support for compiler-synthesized dynamic branch prediction strategies: Rationale and initial results
inferred← citeshttps://doi.org/10.1109/ipps.1997.580974openalex-snapshot
Conflict-free access to multiple single-ported register files
inferred← citeshttps://doi.org/10.1109/micro.1993.282748openalex-snapshot
An evaluation of bottom-up and top-down thread generation techniques
inferred← citeshttps://doi.org/10.1109/micro.1993.282754openalex-snapshot
An analysis of dynamic scheduling techniques for symbolic applications
inferred← citeshttps://doi.org/10.1109/micro.1994.717409openalex-snapshot
Height reduction of control recurrences for ILP processors
inferred← citeshttps://doi.org/10.1109/micro.1994.717412openalex-snapshot
Iterative module scheduling: an algorithm for software pipelining loops
inferred← citeshttps://doi.org/10.1109/micro.1995.476818openalex-snapshot
Modulo scheduling with multiple initiation intervals
inferred← citeshttps://doi.org/10.1109/micro.1995.476825openalex-snapshot
Register allocation for predicated code
inferred← citeshttps://doi.org/10.1109/micro.1995.476843openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferred← citeshttps://doi.org/10.1109/micro.1996.566462openalex-snapshot
Instruction fetch mechanisms for VLIW architectures with compressed encodings
inferred← citeshttps://doi.org/10.1109/micro.2002.1176242openalex-snapshot
Reduced code size modulo scheduling in the absence of hardware support
inferred← citeshttps://doi.org/10.1109/pact.1998.727184openalex-snapshot
A fast interrupt handling scheme for VLIW processors
inferred← citeshttps://doi.org/10.1109/pact.2000.888255openalex-snapshot
Register queues: a new hardware/software approach to efficient software pipelining
inferred← citeshttps://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferred← citeshttps://doi.org/10.1145/173262.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferred← citeshttps://doi.org/10.1145/1749603.1749604openalex-snapshot
Compiling for reconfigurable computing
inferred← citeshttps://doi.org/10.1145/192724.192729openalex-snapshot
Height reduction of control recurrences for ILP processors
inferred← citeshttps://doi.org/10.1145/223982.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors
inferred← citeshttps://doi.org/10.1145/225830.225965openalex-snapshot
A comparison of full and partial predicated execution support for ILP processors
inferred← citeshttps://doi.org/10.1145/231379.231386openalex-snapshot
A reduced multipipeline machine description that preserves scheduling constraints
inferred← citeshttps://doi.org/10.1145/249069.231386openalex-snapshot
A reduced multipipeline machine description that preserves scheduling constraints
inferred← citeshttps://doi.org/10.1145/258492.258518openalex-snapshot
From algorithm parallelism to instruction-level parallelism
inferred← citeshttps://doi.org/10.1145/258915.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/258916.258933openalex-snapshot
Efficient formulation for optimal modulo schedulers
inferred← citeshttps://doi.org/10.1145/2591635.2667171openalex-snapshot
Optimum modulo schedules for minimum register requirements
inferred← citeshttps://doi.org/10.1145/263580.263584openalex-snapshot
Scalable instruction-level parallelism through tree-instructions
inferred← citeshttps://doi.org/10.1145/305138.305226openalex-snapshot
Resource usage models for instruction scheduling
inferred← citeshttps://doi.org/10.1145/3200920openalex-snapshot
Survey on Combinatorial Register Allocation and Instruction Scheduling
inferred← citeshttps://doi.org/10.1145/362652.362658openalex-snapshot
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
inferred← citeshttps://doi.org/10.19153/cleiej.15.2.3openalex-snapshot
Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor
inferred← citeshttps://doi.org/10.3233/emc-2005-00043openalex-snapshot
Reducing code size in VLIW instruction scheduling
inferred← citeshttps://doi.org/10.5555/225160.225180openalex-snapshot
Modulo scheduling with multiple initiation intervals
inferred← citeshttps://doi.org/10.5555/225160.225192openalex-snapshot
Register allocation for predicated code
inferred← citeshttps://doi.org/10.5555/225160.225210openalex-snapshot
Stage scheduling: a technique to reduce the register requirements of a module schedule
inferred← citeshttps://doi.org/10.5555/243846.243886openalex-snapshot
Instruction fetch mechanisms for VLIW architectures with compressed encodings
inferred← citeshttps://doi.org/10.5555/255235.255260openalex-snapshot
Dynamically scheduled VLIW processors
inferred← citeshttps://doi.org/10.5555/255235.255270openalex-snapshot
An evaluation of bottom-up and top-down thread generation techniques
inferred← citeshttps://doi.org/10.5555/255235.255275openalex-snapshot
Predictability of load/store instruction latencies
inferred← citeshttps://doi.org/10.5555/255235.255284openalex-snapshot
An analysis of dynamic scheduling techniques for symbolic applications
inferred← citeshttps://doi.org/10.5555/517554.825787openalex-snapshot
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining
inferred← citeshttps://doi.org/10.5555/522344.825669openalex-snapshot
A fast interrupt handling scheme for VLIW processors
inferred← citeshttps://doi.org/10.5555/774861.774873openalex-snapshot
Reduced code size modulo scheduling in the absence of hardware support
inferred← citeshttps://doi.org/10.5555/776261.776276openalex-snapshot
Inlining of mathematical functions in HP-UX for Itanium® 2
inferred← citeshttps://doi.org/10.6100/ir808001openalex-snapshot
Compiler Strategies for Transport Triggered Architectures.
inferred← citeshttps://doi.org/10.7907/z9t151p8openalex-snapshot
Compiler Techniques for Loosely-Coupled Multi-Cluster Architectures
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