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A theory of generic interpreters

https://doi.org/10.1007/bfb0021719
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-97226-9_24openalex-snapshot
Reasoning about state machines in higher-order logic
inferredcites →https://doi.org/10.1007/978-1-4612-3658-0_1openalex-snapshot
Correctness Properties of the Viper Block Model: The Second Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot
HOL: A Proof Generating System for Higher-Order Logic
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_9openalex-snapshot
Abstraction Mechanisms for Hardware Verification
inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot
Microprocessor design verification
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50019-xopenalex-snapshot
Abstract Theories in HOL
inferredcites →https://doi.org/10.1109/risp.1990.63863openalex-snapshot
A hierarchical methodology for verifying microprogrammed microprocessors
inferredcites →https://doi.org/10.48456/tr-122openalex-snapshot
Temporal abstraction of digital designs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferred← citeshttps://doi.org/10.1007/3-540-58450-1_59openalex-snapshot
Specifying instruction-set architectures in HOL: A primer
inferred← citeshttps://doi.org/10.1007/3-540-59047-1_41openalex-snapshot
A correctness model for pipelined microprocessors
inferred← citeshttps://doi.org/10.1007/3-540-60275-5_78openalex-snapshot
A hierarchical method for reasoning about distributed programming languages
inferred← citeshttps://doi.org/10.1007/3-540-61254-8_30openalex-snapshot
Abstraction of hardware construction
inferred← citeshttps://doi.org/10.1007/3-540-63533-5_24openalex-snapshot
Formal verification of transformations for peephole optimization
inferred← citeshttps://doi.org/10.1007/978-3-540-73859-6_20openalex-snapshot
Algebraic Models of Simultaneous Multithreaded and Multi-core Processors
inferred← citeshttps://doi.org/10.1007/bfb0031820openalex-snapshot
An algebraic model of correctness for superscalar microprocessors
inferred← citeshttps://doi.org/10.1007/bfb0031821openalex-snapshot
Mechanically checking a lemma used in an automatic verification tool
inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot
Algebraic Models of Correctness for Microprocessors
inferred← citeshttps://doi.org/10.1007/s002360050051openalex-snapshot
Algebraic models of microprocessors architecture and organisation
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50019-xopenalex-snapshot
Abstract Theories in HOL
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50038-3openalex-snapshot
Simulating Microprocessors from Formal Specifications11This research was supported in part by NSF under Research Initiation Grant MIP-9109618.
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1109/aspdac.1995.486362openalex-snapshot
Verifying pipelined microprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1997.663181openalex-snapshot
Verification of a distributed computing system by layered proofs
inferred← citeshttps://doi.org/10.48456/tr-512openalex-snapshot
An algebraic framework for modelling and verifying microprocessors using HOL
inferred← citeshttps://doi.org/10.48456/tr-548openalex-snapshot
Formal verification of the ARM6 micro-architecture
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