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Mechanically checking a lemma used in an automatic verification tool

https://doi.org/10.1007/bfb0031821
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-59047-1_50openalex-snapshot
Effective theorem proving for hardware verification
inferredcites →https://doi.org/10.1007/978-1-4471-3558-6_12openalex-snapshot
Using Transformations and Verification in Circuit Design
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot
HOL: A Proof Generating System for Higher-Order Logic
inferredcites →https://doi.org/10.1007/bf00122419openalex-snapshot
Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods
inferredcites →https://doi.org/10.1007/bf01384073openalex-snapshot
Using transformations and verification in circuit design
inferredcites →https://doi.org/10.1007/bfb0021719openalex-snapshot
A theory of generic interpreters
inferredcites →https://doi.org/10.1007/bfb0031806openalex-snapshot
Self-consistency checking
inferredcites →https://doi.org/10.1007/bfb0031807openalex-snapshot
Inverting the abstraction mapping: A methodology for hardware verification
inferredcites →https://doi.org/10.1017/cbo9780511569845.004openalex-snapshot
Hardware Verification using Higher Order Logic
inferredcites →https://doi.org/10.1109/12.368009openalex-snapshot
Formal modeling and verification of microprocessors
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/aspdac.1995.486361openalex-snapshot
Applying formal verification to a commercial microprocessor
inferredcites →https://doi.org/10.1109/aspdac.1995.486362openalex-snapshot
Verifying pipelined microprocessors
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1109/isca.1994.288140openalex-snapshot
The Stanford FLASH multiprocessor
inferredcites →https://doi.org/10.1145/191995.192056openalex-snapshot
The Stanford FLASH multiprocessor
inferredcites →https://doi.org/10.1145/240518.240623openalex-snapshot
Techniques for verifying superscalar microprocessors
inferredcites →https://doi.org/10.11575/prism/30386openalex-snapshot
PROVING A COMPUTER CORRECT IN HIGHER ORDER LOGIC
inferredcites →https://doi.org/10.2307/2266170openalex-snapshot
A formulation of the simple theory of types
inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot
Efficient validity checking for processor verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/10722167_24openalex-snapshot
Formal Verification of VLIW Microprocessors with Speculative Execution
inferred← citeshttps://doi.org/10.1007/3-540-44585-4_20openalex-snapshot
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations
inferred← citeshttps://doi.org/10.1007/3-540-45319-9_18openalex-snapshot
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
inferred← citeshttps://doi.org/10.1007/3-540-45645-7_7openalex-snapshot
Verifying a Simple Pipelined Microprocessor Using Maude
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_18openalex-snapshot
Formal Verification of Designs with Complex Control by Symbolic Simulation
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_5openalex-snapshot
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
inferred← citeshttps://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_2openalex-snapshot
Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_3openalex-snapshot
Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
inferred← citeshttps://doi.org/10.1007/3-540-63166-6_36openalex-snapshot
Trace table based approach for pipelined microprocessor verification
inferred← citeshttps://doi.org/10.1007/3-540-63875-x_40openalex-snapshot
Verification of pipelined microprocessors by comparing memory execution sequences in symbolic simulation
inferred← citeshttps://doi.org/10.1007/978-3-540-73859-6_20openalex-snapshot
Algebraic Models of Simultaneous Multithreaded and Multi-core Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
Machine Assisted Verification
inferred← citeshttps://doi.org/10.1007/bfb0028737openalex-snapshot
Formal verification of out-of-order execution using incremental flushing
inferred← citeshttps://doi.org/10.1007/bfb0028740openalex-snapshot
Processor verification with precise exceptions and speculative execution
inferred← citeshttps://doi.org/10.1007/bfb0031795openalex-snapshot
Formal Methods in Computer-Aided Design
inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot
Algebraic Models of Correctness for Microprocessors
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1023/a:1008622002590openalex-snapshot
A Practical Methodology for the Formal Verification of RISC Processors
inferred← citeshttps://doi.org/10.1023/a:1014118529369openalex-snapshot
Formal Verification of Out-of-Order Execution with Incremental Flushing
inferred← citeshttps://doi.org/10.1109/csd.1998.657552openalex-snapshot
Verification of pipelined microprocessors by correspondence checking in symbolic ternary simulation
inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot
Integrating Formal Verification into an Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.1145/337292.337331openalex-snapshot
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.26083/tuprints-00000113openalex-snapshot
Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
inferred← citeshttps://doi.org/10.48456/tr-548openalex-snapshot
Formal verification of the ARM6 micro-architecture
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