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Algebraic Models of Correctness for Microprocessors

https://doi.org/10.1007/pl00003936
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-49254-2openalex-snapshot
Prospects for Hardware Foundations
inferredcites →https://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferredcites →https://doi.org/10.1007/3-540-49519-3_2openalex-snapshot
Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution
inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-59047-1_41openalex-snapshot
A correctness model for pipelined microprocessors
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_4openalex-snapshot
Formal Verification and Implementation of a Microprocessor
inferredcites →https://doi.org/10.1007/978-1-4615-3576-8openalex-snapshot
The SECD Microprocessor
inferredcites →https://doi.org/10.1007/978-3-642-76771-5openalex-snapshot
Universal Algebra for Computer Scientists
inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot
Microprocessor design verification
inferredcites →https://doi.org/10.1007/bfb0021719openalex-snapshot
A theory of generic interpreters
inferredcites →https://doi.org/10.1007/bfb0021724openalex-snapshot
DDD-FM9001: Derivation of a verified microprocessor
inferredcites →https://doi.org/10.1007/bfb0028737openalex-snapshot
Formal verification of out-of-order execution using incremental flushing
inferredcites →https://doi.org/10.1007/bfb0031807openalex-snapshot
Inverting the abstraction mapping: A methodology for hardware verification
inferredcites →https://doi.org/10.1007/bfb0031820openalex-snapshot
An algebraic model of correctness for superscalar microprocessors
inferredcites →https://doi.org/10.1007/bfb0031821openalex-snapshot
Mechanically checking a lemma used in an automatic verification tool
inferredcites →https://doi.org/10.1007/bfb0031822openalex-snapshot
Automatic generation of invariants in processor verification
inferredcites →https://doi.org/10.1007/s002360050051openalex-snapshot
Algebraic models of microprocessors architecture and organisation
inferredcites →https://doi.org/10.1016/s1571-0661(04)00035-0openalex-snapshot
Fast matching in combinations of regular equational theories
inferredcites →https://doi.org/10.1016/s1571-0661(04)00037-4openalex-snapshot
Reflection and Strategies in Rewriting Logic1 1Supported by Office of Naval Research Contracts N00014-95-C-0225 and N00014-96-C-0114, National Science Foundation Grant CCR-9224005, and by the Information Technology Promotion Agency, Japan, as a part of the Industrial Science and Technology…
inferredcites →https://doi.org/10.1017/cbo9780511569845openalex-snapshot
Higher Order Logic and Hardware Verification
inferredcites →https://doi.org/10.1093/comjnl/6.4.308openalex-snapshot
The Mechanical Evaluation of Expressions
inferredcites →https://doi.org/10.1098/rsta.1992.0022openalex-snapshot
Designing chips that work
inferredcites →https://doi.org/10.1098/rsta.1992.0024openalex-snapshot
A formal HDL and its use in the FM9001 verification
inferredcites →https://doi.org/10.1098/rsta.1992.0030openalex-snapshot
Occam in the specification and verification of microprocessors
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/icfem.1997.630421openalex-snapshot
Systematic formal verification of interpreters
inferredcites →https://doi.org/10.1109/mdt.1987.295161openalex-snapshot
1987 Design Automation Conference
inferredcites →https://doi.org/10.1109/wift.1995.515475openalex-snapshot
Formal verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods
inferredcites →https://doi.org/10.1145/240518.240623openalex-snapshot
Techniques for verifying superscalar microprocessors
inferredcites →https://doi.org/10.1145/873684.873697openalex-snapshot
The computer science laboratory
inferredcites →https://doi.org/10.11575/prism/30398openalex-snapshot
VERIFYING SECD IN HOL
inferredcites →https://doi.org/10.31114/2078-7707-2021-3-65-70openalex-snapshot
On the formal specification of digital systems
inferredcites →https://doi.org/10.48456/tr-41openalex-snapshot
LCF_LSM, A system for specifying and verifying hardware

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-36126-x_8openalex-snapshot
Relating Multi-step and Single-Step Microprocessor Correctness Statements
inferred← citeshttps://doi.org/10.1007/3-540-45645-7_7openalex-snapshot
Verifying a Simple Pipelined Microprocessor Using Maude
inferred← citeshttps://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferred← citeshttps://doi.org/10.1007/978-3-030-92124-8_12openalex-snapshot
Parallelized Sequential Composition and Hardware Weak Memory Models
inferred← citeshttps://doi.org/10.1007/978-3-540-30494-4_9openalex-snapshot
Synchronization-at-Retirement for Pipeline Verification
inferred← citeshttps://doi.org/10.1007/bfb0031820openalex-snapshot
An algebraic model of correctness for superscalar microprocessors
inferred← citeshttps://doi.org/10.1007/s00165-011-0182-7openalex-snapshot
The data type of spatial objects
inferred← citeshttps://doi.org/10.1007/s10009-002-0087-0openalex-snapshot
A framework for superscalar microprocessor correctness statements
inferred← citeshttps://doi.org/10.1016/j.amc.2009.04.058openalex-snapshot
Unifying computers and dynamical systems using the theory of synchronous concurrent algorithms
inferred← citeshttps://doi.org/10.1016/j.jlap.2007.07.001openalex-snapshot
Algebraic models of behaviour and correctness of SMT and CMT processors
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1109/ucc.2012.46openalex-snapshot
Algebraic Specifications of Computing as a Service with Applications to Cost Analysis
inferred← citeshttps://doi.org/10.48456/tr-545openalex-snapshot
A HOL specification of the ARM instruction set architecture
inferred← citeshttps://doi.org/10.48456/tr-548openalex-snapshot
Formal verification of the ARM6 micro-architecture
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