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DDD-FM9001: Derivation of a verified microprocessor

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-97226-9_33openalex-snapshot

Manipulating logical organization with system factorizations

inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot

FM8501: A Verified Microprocessor

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot

VLSI Specification, Verification and Synthesis

inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_12openalex-snapshot

A Tactical Framework for Hardware Design

inferredcites →https://doi.org/10.1016/0378-4754(89)90181-xopenalex-snapshot

A computational logic handbook

inferredcites →https://doi.org/10.1016/b978-0-444-81641-2.50016-2openalex-snapshot

Integrating Boolean Verification with Formal Derivation††Research reported herein was supported, in part, by NSF: The National Science Foundation, under grants numbered DCR 85-21497, MIP 87-07067 and MIP 89-21842, and by NASA: The National Aeronautics and Space Administration under grant number…

inferredcites →https://doi.org/10.1016/b978-0-444-81641-2.50020-4openalex-snapshot

Toward a Basis for Protocol Specification and Process Decomposition ††This research was supported in part by the National Science Foundation under grants numbered MIP 8921842 and MIP 9208745.

inferredcites →https://doi.org/10.1016/c2013-0-10412-6openalex-snapshot

A Computational Logic Handbook

inferredcites →https://doi.org/10.1098/rsta.1992.0024openalex-snapshot

A formal HDL and its use in the FM9001 verification

inferredcites →https://doi.org/10.1109/dac.1979.1600139openalex-snapshot

The Application of Program Verification to Hardware Verification

inferredcites →https://doi.org/10.1109/tc.1978.1675141openalex-snapshot

Binary Decision Diagrams

inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot

Graph-Based Algorithms for Boolean Function Manipulation

inferredcites →https://doi.org/10.1145/37888.37890openalex-snapshot

COSMOS: a compiled simulator for MOS circuits

inferredcites →https://doi.org/10.5555/285730.285784openalex-snapshot

Tutorial on high-level synthesis

inferredcites →https://doi.org/10.5555/800292.811742openalex-snapshot

The application of program verification techniques to hardware verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-40922-x_32openalex-snapshot

Visualizing System Factorizations with Behavior Tables

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A Systematic Incrementalization Technique and Its Application to Hardware Design

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Algebraic Models of Superscalar Microprocessor Implementations: a Case Study

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Formal design of a class of computers — its high stage: abstract microprogramming

inferred← citeshttps://doi.org/10.1007/3-540-61254-8_30openalex-snapshot

Abstraction of hardware construction

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Integrated Reasoning Support in System Design: Design Derivation and Theorem Proving

inferred← citeshttps://doi.org/10.1007/b95732openalex-snapshot

Higher-Level Hardware Synthesis

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Algebraic models and the correctness of microprocessors

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A tutorial on digital design derivation using DRS

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Formal synthesis in circuit design — A classification and survey

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An algebraic model of correctness for superscalar microprocessors

inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot

Algebraic Models of Correctness for Microprocessors

inferred← citeshttps://doi.org/10.1007/s002360050051openalex-snapshot

Algebraic models of microprocessors architecture and organisation

inferred← citeshttps://doi.org/10.1007/s100090100067openalex-snapshot

A systematic incrementalization technique and its application to hardware design

inferred← citeshttps://doi.org/10.1016/s1474-6670(17)44819-1openalex-snapshot

DRS - Derivational Reasoning System: A Digital Design Derivation System for Hardware Synthesis *

inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot

Algebraic models of correctness for abstract pipelines

inferred← citeshttps://doi.org/10.1023/a:1007715101339openalex-snapshot

inferred← citeshttps://doi.org/10.1023/a:1008685826293openalex-snapshot

The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor

inferred← citeshttps://doi.org/10.1109/aspdac.1995.486381openalex-snapshot

The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor

inferred← citeshttps://doi.org/10.1109/cmpass.1995.521893openalex-snapshot

NASA Langley's research and technology-transfer program in formal methods

inferred← citeshttps://doi.org/10.1109/glsv.1995.516030openalex-snapshot

Specification and synthesis of bounded indirection

inferred← citeshttps://doi.org/10.1109/iccd.1993.393334openalex-snapshot

System factorization in codesign. A case study of the use of formal techniques to achieve hardware-software decomposition

inferred← citeshttps://doi.org/10.1109/iccd.1993.393338openalex-snapshot

Derivation of a DRAM memory interface by sequential decomposition

inferred← citeshttps://doi.org/10.1109/reldis.1994.336902openalex-snapshot

Interaction of formal design systems in the development of a fault-tolerant clock synchronization circuit

inferred← citeshttps://doi.org/10.1145/2543581.2543588openalex-snapshot

Synchronous digital circuits as functional programs

inferred← citeshttps://doi.org/10.1145/262004.262007openalex-snapshot

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

inferred← citeshttps://doi.org/10.14236/ewic/dcc1996.9openalex-snapshot

Verification of an Optimized Fault-Tolerant Clock Synchronization Circuit

inferred← citeshttps://doi.org/10.25911/5d78d9f7865dbopenalex-snapshot

Arrows for knowledge-based circuits

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Fault behavior dictionary for simulation of device-level transients

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Behavior tables: a basis for system representation and transformational system synthesis

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