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Formal synthesis in circuit design — A classification and survey
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/0-387-97226-9_26openalex-snapshot
Behavior-preserving transformations for high-level synthesis
inferredcites →https://doi.org/10.1007/0-387-97226-9_33openalex-snapshot
Manipulating logical organization with system factorizations
inferredcites →https://doi.org/10.1007/3-540-58450-1_50openalex-snapshot
An engineering approach to formal digital system design
inferredcites →https://doi.org/10.1007/3-540-59047-1_51openalex-snapshot
A formal framework for high level synthesis
inferredcites →https://doi.org/10.1007/3-540-59047-1_55openalex-snapshot
Quantitative evaluation of formal based synthesis in ASIC design
inferredcites →https://doi.org/10.1007/3-540-60275-5openalex-snapshot
Higher Order Logic Theorem Proving and Its Applications
inferredcites →https://doi.org/10.1007/3-540-60275-5_63openalex-snapshot
An automata theory dedicated towards formal circuit synthesis
inferredcites →https://doi.org/10.1007/3-540-60385-9_5openalex-snapshot
Formally embedding existing high level synthesis algorithms
inferredcites →https://doi.org/10.1007/978-1-4471-3558-6_12openalex-snapshot
Using Transformations and Verification in Circuit Design
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4openalex-snapshot
VLSI Specification, Verification and Synthesis
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_12openalex-snapshot
A Tactical Framework for Hardware Design
inferredcites →https://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferredcites →https://doi.org/10.1007/bf01384073openalex-snapshot
Using transformations and verification in circuit design
inferredcites →https://doi.org/10.1007/bf01607881openalex-snapshot
High level synthesis and generating FPGAs with the BEDROC system
inferredcites →https://doi.org/10.1007/bfb0021724openalex-snapshot
DDD-FM9001: Derivation of a verified microprocessor
inferredcites →https://doi.org/10.1007/bfb0105403openalex-snapshot
Implementation issues about the embedding of existing high level synthesis algorithms in HOL
inferredcites →https://doi.org/10.1016/0167-9260(91)90048-popenalex-snapshot
Formally verified synthesis of combinational CMOS circuits
inferredcites →https://doi.org/10.1016/b978-0-444-81641-2.50024-1openalex-snapshot
Transformational Rewriting with Ruby
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50034-6openalex-snapshot
Deriving a Correct Computer
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50035-8openalex-snapshot
Formal Tools for Tri-State Design in Busses
inferredcites →https://doi.org/10.1016/b978-0-444-89880-7.50036-xopenalex-snapshot
Specification and formal synthesis of digital circuits
inferredcites →https://doi.org/10.1093/comjnl/38.2.101openalex-snapshot
An engineering approach to formal digital system design
inferredcites →https://doi.org/10.1098/rsta.1992.0025openalex-snapshot
Using Nuprl for the verification and synthesis of hardware
inferredcites →https://doi.org/10.1098/rsta.1992.0029openalex-snapshot
Dependent types and formal synthesis
inferredcites →https://doi.org/10.1109/32.469458openalex-snapshot
Verifying a logic-synthesis algorithm and implementation: a case study in software verification
inferredcites →https://doi.org/10.1109/43.124396openalex-snapshot
A prescriptive formal model for data-path hardware
inferredcites →https://doi.org/10.1109/43.31537openalex-snapshot
Using statecharts for hardware description and synthesis
inferredcites →https://doi.org/10.1109/5.52214openalex-snapshot
The high-level synthesis of digital systems
inferredcites →https://doi.org/10.1109/asic.1991.242955openalex-snapshot
The BEDROC high level synthesis system
inferredcites →https://doi.org/10.1109/edtc.1996.494119openalex-snapshot
Exploiting functional dependencies in finite state machine verification
inferredcites →https://doi.org/10.1109/eurmic.1994.390403openalex-snapshot
High level synthesis based on formal methods
inferredcites →https://doi.org/10.1109/glsv.1996.497633openalex-snapshot
On verifying the correctness of retimed circuits
inferredcites →https://doi.org/10.1109/iccd.1991.139915openalex-snapshot
A formally verified system for logic synthesis
inferredcites →https://doi.org/10.1109/iccd.1993.393338openalex-snapshot
Derivation of a DRAM memory interface by sequential decomposition
inferredcites →https://doi.org/10.5555/787259.787608openalex-snapshot
Exploiting functional dependencies in finite state machine verification
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-40922-x_32openalex-snapshot
Visualizing System Factorizations with Behavior Tables
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_19openalex-snapshot
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_15openalex-snapshot
Formal Synthesis at the Algorithmic Level
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_16openalex-snapshot
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
inferred← citeshttps://doi.org/10.1007/978-1-4757-4419-4_5openalex-snapshot
Automatic Formal Derivation Applied to High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/978-3-540-79299-4_1openalex-snapshot
Formalization of Data Flow Computing and a Coinductive Approach to Verifying Flowware Synthesis
inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
Machine Assisted Verification
inferred← citeshttps://doi.org/10.1007/s00165-007-0028-5openalex-snapshot
Proof producing synthesis of arithmetic and cryptographic hardware
inferred← citeshttps://doi.org/10.1007/s00165-012-0223-xopenalex-snapshot
Automatic verification of reduction techniques in Higher Order Logic
inferred← citeshttps://doi.org/10.1109/43.739056openalex-snapshot
On the efficiency of formal synthesis-experimental results
inferred← citeshttps://doi.org/10.1109/csd.2001.981772openalex-snapshot
Embedding imperative synchronous languages in interactive theorem provers
inferred← citeshttps://doi.org/10.1109/date.1998.655997openalex-snapshot
Correct high-level synthesis: a formal perspective
inferred← citeshttps://doi.org/10.1109/date.1999.761097openalex-snapshot
Automatic verification of scheduling results in high-level synthesis
inferred← citeshttps://doi.org/10.1109/edtc.1997.582395openalex-snapshot
A constructive approach towards correctness of synthesis-application within retiming
inferred← citeshttps://doi.org/10.1109/eurmic.1998.711770openalex-snapshot
Design correctness of digital systems
inferred← citeshttps://doi.org/10.1109/eurmic.1998.711771openalex-snapshot
Performing high-level synthesis via program transformations within a theorem prover
inferred← citeshttps://doi.org/10.1109/fmcad.2015.7542251openalex-snapshot
Formal verification of automatic circuit transformations for fault-tolerance
inferred← citeshttps://doi.org/10.1109/hase.2015.13openalex-snapshot
Verilog Synthesis in the Higher-Order Transformation Framework of TL
inferred← citeshttps://doi.org/10.1109/hldvt.2000.889564openalex-snapshot
An approach to high-level synthesis system validation using formally verified transformations
inferred← citeshttps://doi.org/10.1109/isqed.2013.6523660openalex-snapshot
Efficient translation validation of high-level synthesis
inferred← citeshttps://doi.org/10.1109/isss.1997.621670openalex-snapshot
An efficient representation for formal synthesis
inferred← citeshttps://doi.org/10.1109/mwscas.2005.1594049openalex-snapshot
Symbolic verification of synthesized RTL using Boolean satisfiability and uninterpreted RTL transformations
inferred← citeshttps://doi.org/10.1109/mwscas.2007.4488591openalex-snapshot
Automated formal synthesis of Wallace Tree multipliers
inferred← citeshttps://doi.org/10.1109/tcad.2007.913390openalex-snapshot
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2397036openalex-snapshot
Source Code Error Detection in High-Level Synthesis Functional Verification
inferred← citeshttps://doi.org/10.1145/307418.307449openalex-snapshot
Automatic verification of scheduling results in high-level synthesis
inferred← citeshttps://doi.org/10.1145/307988.307989openalex-snapshot
Formal verification in hardware design
inferred← citeshttps://doi.org/10.1145/996566.996584openalex-snapshot
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis
inferred← citeshttps://doi.org/10.5555/261693.261699openalex-snapshot
An efficient representation for formal synthesis
inferred← citeshttps://doi.org/10.5555/368058.368559openalex-snapshot
Correct high-level synthesis: a formal perspective
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