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Decomposing the proof of correctness of pipelined microprocessors

https://doi.org/10.1007/bfb0028739
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-59047-1_50openalex-snapshot
Effective theorem proving for hardware verification
inferredcites →https://doi.org/10.1007/3-540-63166-6_36openalex-snapshot
Trace table based approach for pipelined microprocessor verification
inferredcites →https://doi.org/10.1007/bf00122419openalex-snapshot
Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods
inferredcites →https://doi.org/10.1007/bfb0031807openalex-snapshot
Inverting the abstraction mapping: A methodology for hardware verification
inferredcites →https://doi.org/10.1007/bfb0031808openalex-snapshot
Validity checking for combinations of theories with equality
inferredcites →https://doi.org/10.1109/32.345827openalex-snapshot
Formal verification for fault-tolerant architectures: prolegomena to the design of PVS
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1145/240518.240623openalex-snapshot
Techniques for verifying superscalar microprocessors
inferredcites →https://doi.org/10.1145/240518.240624openalex-snapshot
A scalable formal verification methodology for pipelined microprocessors
inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot
Efficient validity checking for processor verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/10722167_24openalex-snapshot
Formal Verification of VLIW Microprocessors with Speculative Execution
inferred← citeshttps://doi.org/10.1007/10722167_39openalex-snapshot
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
inferred← citeshttps://doi.org/10.1007/3-540-36126-x_8openalex-snapshot
Relating Multi-step and Single-Step Microprocessor Correctness Statements
inferred← citeshttps://doi.org/10.1007/3-540-40922-x_11openalex-snapshot
Correctness of Pipelined Machines
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_33openalex-snapshot
A Framework for Microprocessor Correctness Statements
inferred← citeshttps://doi.org/10.1007/3-540-45645-7_7openalex-snapshot
Verifying a Simple Pipelined Microprocessor Using Maude
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_18openalex-snapshot
Formal Verification of Designs with Complex Control by Symbolic Simulation
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_3openalex-snapshot
A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_4openalex-snapshot
Formal Verification of Explicitly Parallel Microprocessors
inferred← citeshttps://doi.org/10.1007/3-540-48683-6_10openalex-snapshot
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study
inferred← citeshttps://doi.org/10.1007/3-540-48683-6_7openalex-snapshot
Proof of Correctness of a Processor with Reorder Buffer Using the Completion Functions Approach
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_2openalex-snapshot
Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_24openalex-snapshot
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
inferred← citeshttps://doi.org/10.1007/978-3-030-16458-4_27openalex-snapshot
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification
inferred← citeshttps://doi.org/10.1007/978-3-642-03429-9_10openalex-snapshot
A Rewriting Logic Approach to Type Inference
inferred← citeshttps://doi.org/10.1007/bfb0028737openalex-snapshot
Formal verification of out-of-order execution using incremental flushing
inferred← citeshttps://doi.org/10.1007/pl00010806openalex-snapshot
Theorem proving in technology transfer: the user’s point of view
inferred← citeshttps://doi.org/10.1007/s10009-002-0087-0openalex-snapshot
A framework for superscalar microprocessor correctness statements
inferred← citeshttps://doi.org/10.1007/s10817-006-9035-0openalex-snapshot
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1023/a:1014118529369openalex-snapshot
Formal Verification of Out-of-Order Execution with Incremental Flushing
inferred← citeshttps://doi.org/10.1023/a:1014122630277openalex-snapshot
Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability
inferred← citeshttps://doi.org/10.1023/a:1014170513439openalex-snapshot
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
inferred← citeshttps://doi.org/10.1023/a:1024716316140openalex-snapshot
Formal Verification of a Complex Pipelined Processor
inferred← citeshttps://doi.org/10.1049/cdt2.12024openalex-snapshot
Modelling and verification of parameterized architectures: A functional approach
inferred← citeshttps://doi.org/10.1080/1206212x.2010.11441963openalex-snapshot
Modelling and Verification of Pipelined Micro-Architectures: Functional Approach
inferred← citeshttps://doi.org/10.1109/aspdac.1999.759989openalex-snapshot
Formal design verification for correctness of pipelined microprocessors with out-of-order instruction execution
inferred← citeshttps://doi.org/10.1109/iccc47050.2019.9064185openalex-snapshot
An Adaptive Multitasking Superscalar Processor
inferred← citeshttps://doi.org/10.1109/iemtronics51293.2020.9216450openalex-snapshot
An Adaptive Overlap-Pipelined Multitasking Superscalar Processor
inferred← citeshttps://doi.org/10.1109/iscas.2009.5118054openalex-snapshot
Verification of desynchronized circuits
inferred← citeshttps://doi.org/10.1109/itng.2008.92openalex-snapshot
A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach
inferred← citeshttps://doi.org/10.1109/memcod.2003.1210090openalex-snapshot
Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions
inferred← citeshttps://doi.org/10.1109/prdc.2002.1185653openalex-snapshot
Formal verification of a pipelined processor with new memory hierarchy using a commercial model checker
inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot
Integrating Formal Verification into an Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.1145/337292.337331openalex-snapshot
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
inferred← citeshttps://doi.org/10.1145/3656019.3676889openalex-snapshot
PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.26083/tuprints-00000113openalex-snapshot
Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
inferred← citeshttps://doi.org/10.3390/electronics8091057openalex-snapshot
Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification
inferred← citeshttps://doi.org/10.48456/tr-512openalex-snapshot
An algebraic framework for modelling and verifying microprocessors using HOL
inferred← citeshttps://doi.org/10.5555/2157654.2157687openalex-snapshot
Desynchronization: Design for verification
inferred← citeshttps://doi.org/10.6083/m4kh0kkxopenalex-snapshot
Structuring instruction-sets with higher-order functions
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