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Inverting the abstraction mapping: A methodology for hardware verification

https://doi.org/10.1007/bfb0031807
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-58179-0_59openalex-snapshot
Ground temporal logic: A logic for hardware verification
inferredcites →https://doi.org/10.1007/3-540-59047-1_50openalex-snapshot
Effective theorem proving for hardware verification
inferredcites →https://doi.org/10.1016/0304-3975(91)90224-popenalex-snapshot
The existence of refinement mappings
inferredcites →https://doi.org/10.1109/32.345827openalex-snapshot
Formal verification for fault-tolerant architectures: prolegomena to the design of PVS

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44577-3_10openalex-snapshot
Abstract Interpretation Based Formal Methods and Future Challenges
inferred← citeshttps://doi.org/10.1007/3-540-45645-7_7openalex-snapshot
Verifying a Simple Pipelined Microprocessor Using Maude
inferred← citeshttps://doi.org/10.1007/3-540-46674-6_14openalex-snapshot
Logical Relations in Circuit Verification
inferred← citeshttps://doi.org/10.1007/3-540-49254-2_5openalex-snapshot
Algebraic Models of Superscalar Microprocessor Implementations: a Case Study
inferred← citeshttps://doi.org/10.1007/3-540-63166-6_6openalex-snapshot
A compositional rule for hardware design refinement
inferred← citeshttps://doi.org/10.1007/978-0-387-35190-2_19openalex-snapshot
Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System
inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
Machine Assisted Verification
inferred← citeshttps://doi.org/10.1007/978-3-642-60858-2_26openalex-snapshot
Machine-Assisted Verification Using Theorem Proving and Model Checking
inferred← citeshttps://doi.org/10.1007/bfb0028739openalex-snapshot
Decomposing the proof of correctness of pipelined microprocessors
inferred← citeshttps://doi.org/10.1007/bfb0031813openalex-snapshot
PVS: Combining specification, proof checking, and model checking
inferred← citeshttps://doi.org/10.1007/bfb0031821openalex-snapshot
Mechanically checking a lemma used in an automatic verification tool
inferred← citeshttps://doi.org/10.1007/pl00003936openalex-snapshot
Algebraic Models of Correctness for Microprocessors
inferred← citeshttps://doi.org/10.1016/s0167-6423(99)00030-1openalex-snapshot
A methodology for hardware verification using compositional model checking
inferred← citeshttps://doi.org/10.1016/s1567-8326(03)00041-9openalex-snapshot
Algebraic models of correctness for abstract pipelines
inferred← citeshttps://doi.org/10.1109/date.1999.761097openalex-snapshot
Automatic verification of scheduling results in high-level synthesis
inferred← citeshttps://doi.org/10.1109/icfem.1997.630421openalex-snapshot
Systematic formal verification of interpreters
inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot
Integrating Formal Verification into an Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.1145/289423.289440openalex-snapshot
Lava
inferred← citeshttps://doi.org/10.1145/307418.307449openalex-snapshot
Automatic verification of scheduling results in high-level synthesis
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
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