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Model checking for a first-order temporal logic using multiway decision graphs

https://doi.org/10.1007/bfb0028747
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
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Ground temporal logic: A logic for hardware verification
inferredcites →https://doi.org/10.1007/3-540-60045-0_43openalex-snapshot
Automatic datapath abstraction in hardware systems
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What if model checking must be truly symbolic
inferredcites →https://doi.org/10.1007/3-540-60385-9_9openalex-snapshot
State enumeration with abstract descriptions of state machines
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VIS: A system for verification and synthesis
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Verifying linear temporal properties of data insensitive controllers using finite instantiations
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A Unified Framework for the Formal Verification of Sequential Circuits
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First-Order-CTL Model Checking
inferredcites →https://doi.org/10.1007/978-3-540-69850-0_12openalex-snapshot
DESIGN AND SYNTHESIS OF SYNCHRONIZATION SKELETONS USING BRANCHING TIME TEMPORAL LOGIC
inferredcites →https://doi.org/10.1007/bfb0028747openalex-snapshot
Model checking for a first-order temporal logic using multiway decision graphs
inferredcites →https://doi.org/10.1007/bfb0028750openalex-snapshot
Computing reachable control states of systems modeled with uninterpreted functions and infinite memory
inferredcites →https://doi.org/10.1007/bfb0031811openalex-snapshot
Formal verification of the Island Tunnel Controller using Multiway Decision Graphs
inferredcites →https://doi.org/10.1007/bfb0042302openalex-snapshot
Reducibility in analysis of coordination
inferredcites →https://doi.org/10.1016/0167-6423(87)90036-0openalex-snapshot
Modalities for model checking: branching time logic strikes back
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/0898-1221(95)90267-8openalex-snapshot
Computer-aided verification of coordinating processes: The automata-theoretic approach
inferredcites →https://doi.org/10.1016/s0304-3975(01)00345-0openalex-snapshot
On the non-termination of MDG-based abstract state enumeration
inferredcites →https://doi.org/10.1023/a:1008663530211openalex-snapshot
Multiway Decision Graphs for Automated Hardware Verification
inferredcites →https://doi.org/10.1109/aspdac.1995.486372openalex-snapshot
Description and verification of RTL designs using multiway decision graphs
inferredcites →https://doi.org/10.1109/aspdac.1995.486385openalex-snapshot
Integrating design and verification environments through a logic supporting hardware diagrams
inferredcites →https://doi.org/10.1109/glsv.1998.665311openalex-snapshot
MDG-based verification by retiming and combinational transformations
inferredcites →https://doi.org/10.1109/iccad.1990.129859openalex-snapshot
A unified framework for the formal verification of sequential circuits
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/143165.143235openalex-snapshot
Model checking and abstraction

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Model Reductions and a Case Study
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Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
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Providing Automated Verification in HOL Using MDGs
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First-Order LTL Model Checking Using MDGs
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First-Order-CTL Model Checking
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A New Approach for the Construction of Multiway Decision Graphs
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LTL Model-Checking for Malware Detection
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LCF-style Platform based on Multiway Decision Graphs
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Hybrid verification integrating HOL theorem proving with MDG model checking
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Model Checking with Abstract Types
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Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization
inferred← citeshttps://doi.org/10.1049/ip-cdt:20040034openalex-snapshot
Formal verification of a SONET data stream processor
inferred← citeshttps://doi.org/10.1093/comjnl/47.1.71openalex-snapshot
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)
inferred← citeshttps://doi.org/10.1109/43.771178openalex-snapshot
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
inferred← citeshttps://doi.org/10.1109/aiccsa.2003.1227503openalex-snapshot
On the embedding of the MDG specification languages in HOL
inferred← citeshttps://doi.org/10.1109/asic.2000.880762openalex-snapshot
Model reductions in MDG-based model checking
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MDG-Based Verification of the Look-Aside Interface
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Hybrid tool integrating HOL theorem proving with MDG model checking
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Integrating SAT with Multiway Decision Graphs for efficient model checking
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Processing APL properties to generate verification-ready MDG model
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Static slicing-based pre-reduction technique for MDG model-checker
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MDGs Reduction Technique Based on the HOL Theorem Prover
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Formal verification of ASM designs using the MDG tool
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Cone of influence and constants propgation reduction techniques for MDG model checker
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Term ordering problem on MDG
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Language emptiness checking using MDGs
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High Level Reduction Technique for Multiway Decision Graphs Based Model Checking
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CONDITIONED SLICING FOR EFFICIENT MULTIWAY DECISION GRAPHS MODEL-CHECKER
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