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Formal verification of the Island Tunnel Controller using Multiway Decision Graphs

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot

Verification of synchronous sequential machines based on symbolic execution

inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot

Automatic verification of pipelined microprocessor control

inferredcites →https://doi.org/10.1007/3-540-58179-0_59openalex-snapshot

Ground temporal logic: A logic for hardware verification

inferredcites →https://doi.org/10.1007/3-540-60385-9_9openalex-snapshot

State enumeration with abstract descriptions of state machines

inferredcites →https://doi.org/10.1007/3-540-61474-5_93openalex-snapshot

Symbolic model checking

inferredcites →https://doi.org/10.1007/3-540-61474-5_95openalex-snapshot

VIS: A system for verification and synthesis

inferredcites →https://doi.org/10.1007/3-540-61474-5_96openalex-snapshot

MDG tools for the verification of RTL designs

inferredcites →https://doi.org/10.1007/978-1-4615-3190-6openalex-snapshot

Symbolic Model Checking

inferredcites →https://doi.org/10.1007/bfb0031811openalex-snapshot

Formal verification of the Island Tunnel Controller using Multiway Decision Graphs

inferredcites →https://doi.org/10.1023/a:1008663530211openalex-snapshot

Multiway Decision Graphs for Automated Hardware Verification

inferredcites →https://doi.org/10.1109/43.275352openalex-snapshot

Symbolic model checking for sequential circuit verification

inferredcites →https://doi.org/10.1109/aspdac.1995.486385openalex-snapshot

Integrating design and verification environments through a logic supporting hardware diagrams

inferredcites →https://doi.org/10.1109/glsv.1996.497603openalex-snapshot

Formal verification of an ATM switch fabric using multiway decision graphs

inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot

Efficient validity checking for processor verification

inferredcites →https://doi.org/10.1109/iccad.1995.480007openalex-snapshot

Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs

inferredcites →https://doi.org/10.1109/iccd.1996.563526openalex-snapshot

Behavioral verification of an ATM switch fabric using implicit abstract state enumeration

inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot

Graph-Based Algorithms for Boolean Function Manipulation

inferredcites →https://doi.org/10.1145/143165.143235openalex-snapshot

Model checking and abstraction

inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot

Verification of arithmetic circuits with binary moment diagrams

inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot

Efficient validity checking for processor verification

inferredcites →https://doi.org/10.5555/224841.224875openalex-snapshot

Hybrid decision diagrams

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Formal Verification of a SONET Telecom System Block

inferred← citeshttps://doi.org/10.1007/3-540-36498-6_16openalex-snapshot

Interfacing ASM with the MDG Tool

inferred← citeshttps://doi.org/10.1007/3-540-49519-3_25openalex-snapshot

Formally Verifying Data and Control with Weak Reachability Invariants

inferred← citeshttps://doi.org/10.1007/3-540-49519-3_30openalex-snapshot

Techniques for Implicit State Enumeration of EFSMs

inferred← citeshttps://doi.org/10.1007/978-0-387-35190-2_15openalex-snapshot

On the Non-Termination of MDG-Based Abstract State Enumeration

inferred← citeshttps://doi.org/10.1007/bfb0028747openalex-snapshot

Model checking for a first-order temporal logic using multiway decision graphs

inferred← citeshttps://doi.org/10.1007/bfb0028750openalex-snapshot

Computing reachable control states of systems modeled with uninterpreted functions and infinite memory

inferred← citeshttps://doi.org/10.1007/s00165-012-0223-xopenalex-snapshot

Automatic verification of reduction techniques in Higher Order Logic

inferred← citeshttps://doi.org/10.1007/s10703-006-0017-yopenalex-snapshot

Providing a formal linkage between MDG and HOL

inferred← citeshttps://doi.org/10.1007/s11390-009-9205-8openalex-snapshot

An Abstract Reachability Approach by Combining HOL Induction and Multiway Decision Graphs

inferred← citeshttps://doi.org/10.1007/s11390-011-9421-xopenalex-snapshot

NuMDG: A New Tool for Multiway Decision Graphs Construction

inferred← citeshttps://doi.org/10.1016/j.entcs.2009.07.012openalex-snapshot

LCF-style Platform based on Multiway Decision Graphs

inferred← citeshttps://doi.org/10.1016/j.mejo.2006.07.019openalex-snapshot

Hybrid verification integrating HOL theorem proving with MDG model checking

inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.03.007openalex-snapshot

Formal verification of ASMs using MDGs

inferred← citeshttps://doi.org/10.1016/s0304-3975(01)00345-0openalex-snapshot

On the non-termination of MDG-based abstract state enumeration

inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80669-8openalex-snapshot

Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization

inferred← citeshttps://doi.org/10.1049/ip-cdt:20040034openalex-snapshot

Formal verification of a SONET data stream processor

inferred← citeshttps://doi.org/10.1093/comjnl/47.1.71openalex-snapshot

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)

inferred← citeshttps://doi.org/10.1109/43.771178openalex-snapshot

Modeling and formal verification of the Fairisle ATM switch fabric using MDGs

inferred← citeshttps://doi.org/10.1109/fdl.2008.4641435openalex-snapshot

The performance of combining multiway decision graphs and HOL theorem prover

inferred← citeshttps://doi.org/10.1109/glsv.1998.665311openalex-snapshot

MDG-based verification by retiming and combinational transformations

inferred← citeshttps://doi.org/10.1109/icm.2004.1434595openalex-snapshot

Hybrid tool integrating HOL theorem proving with MDG model checking

inferred← citeshttps://doi.org/10.1109/icm.2007.4497677openalex-snapshot

Integrating SAT with Multiway Decision Graphs for efficient model checking

inferred← citeshttps://doi.org/10.1109/ismvl.2010.12openalex-snapshot

MDGs Reduction Technique Based on the HOL Theorem Prover

inferred← citeshttps://doi.org/10.1109/sefm.2003.1236223openalex-snapshot

Formal verification of ASM designs using the MDG tool

inferred← citeshttps://doi.org/10.14236/ewic/vecos2007.9openalex-snapshot

High Level Reduction Technique for Multiway Decision Graphs Based Model Checking

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