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Computing reachable control states of systems modeled with uninterpreted functions and infinite memory

https://doi.org/10.1007/bfb0028750
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-55179-4_43openalex-snapshot
Comparing generic state machines
inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-60045-0_43openalex-snapshot
Automatic datapath abstraction in hardware systems
inferredcites →https://doi.org/10.1007/3-540-61474-5_95openalex-snapshot
VIS: A system for verification and synthesis
inferredcites →https://doi.org/10.1007/bfb0031810openalex-snapshot
Verification using uninterpreted functions and finite instantiations
inferredcites →https://doi.org/10.1007/bfb0031811openalex-snapshot
Formal verification of the Island Tunnel Controller using Multiway Decision Graphs
inferredcites →https://doi.org/10.1023/a:1008663530211openalex-snapshot
Multiway Decision Graphs for Automated Hardware Verification
inferredcites →https://doi.org/10.1109/12.250616openalex-snapshot
Automated verification of behavioral equivalence for microprocessors
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/aspdac.1995.486385openalex-snapshot
Integrating design and verification environments through a logic supporting hardware diagrams
inferredcites →https://doi.org/10.1109/iccad.1995.479877openalex-snapshot
Efficient validity checking for processor verification
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1145/322123.322137openalex-snapshot
A Practical Decision Procedure for Arithmetic with Function Symbols
inferredcites →https://doi.org/10.1145/322186.322198openalex-snapshot
Fast Decision Procedures Based on Congruence Closure
inferredcites →https://doi.org/10.5555/224841.224849openalex-snapshot
Efficient validity checking for processor verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/scj.1091openalex-snapshot
Efficient verification by exploiting symmetry and abstraction
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_5openalex-snapshot
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic
inferred← citeshttps://doi.org/10.1007/978-3-540-39724-3_31openalex-snapshot
Convergence Testing in Term-Level Bounded Model Checking
inferred← citeshttps://doi.org/10.1007/978-3-540-49382-2_27openalex-snapshot
First-Order-CTL Model Checking
inferred← citeshttps://doi.org/10.1007/978-3-540-88387-6_28openalex-snapshot
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic
inferred← citeshttps://doi.org/10.1007/bfb0028747openalex-snapshot
Model checking for a first-order temporal logic using multiway decision graphs
inferred← citeshttps://doi.org/10.1093/comjnl/47.1.71openalex-snapshot
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)
inferred← citeshttps://doi.org/10.1109/dac.1999.781348openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1109/iccad.2005.1560218openalex-snapshot
Scalable compositional minimization via static analysis
inferred← citeshttps://doi.org/10.1109/memcod.2003.1210090openalex-snapshot
Formal verification of an Intel XScale processor model with scoreboarding, specialized execution pipelines, and impress data-memory exceptions
inferred← citeshttps://doi.org/10.1109/prdc.2001.992695openalex-snapshot
Partial order reduction in verification of wheel structured parameterized circuits
inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot
Integrating Formal Verification into an Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.1145/288548.289082openalex-snapshot
Formal verification of pipeline control using controlled token nets and abstract interpretation
inferred← citeshttps://doi.org/10.1145/309847.309967openalex-snapshot
Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors
inferred← citeshttps://doi.org/10.1504/ijes.2005.008815openalex-snapshot
TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.21236/ada461050openalex-snapshot
Convergence Testing in Term-Level Bounded Model Checking
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.3.105openalex-snapshot
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic
inferred← citeshttps://doi.org/10.2197/ipsjtsldm.3.268openalex-snapshot
Approximate Model Checking Using a Subset of First-order Logic
inferred← citeshttps://doi.org/10.5555/1129601.1129749openalex-snapshot
Scalable compositional minimization via static analysis
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