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Verification of floating-point adders

https://doi.org/10.1007/bfb0028769
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-61474-5_93openalex-snapshot
Symbolic model checking
inferredcites →https://doi.org/10.1007/978-1-4615-0292-0_4openalex-snapshot
A Unified Framework for the Formal Verification of Sequential Circuits
inferredcites →https://doi.org/10.1007/978-1-4615-3190-6openalex-snapshot
Symbolic Model Checking
inferredcites →https://doi.org/10.1007/bfb0028769openalex-snapshot
Verification of floating-point adders
inferredcites →https://doi.org/10.1007/bfb0031797openalex-snapshot
Verification of all circuits in a floating-point unit using word-level model checking
inferredcites →https://doi.org/10.1007/bfb0031816openalex-snapshot
ACL2 theorems about commercial microprocessors
inferredcites →https://doi.org/10.1016/b978-0-12-627230-7.50021-5openalex-snapshot
Floating-Point Math
inferredcites →https://doi.org/10.1109/4.508263openalex-snapshot
Leading-zero anticipatory logic for high-speed floating point addition
inferredcites →https://doi.org/10.1109/43.298036openalex-snapshot
Efficient symbolic simulation-based verification using the parametric form of Boolean expressions
inferredcites →https://doi.org/10.1109/iccad.1990.129859openalex-snapshot
A unified framework for the formal verification of sequential circuits
inferredcites →https://doi.org/10.1109/iccad.1995.479995openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.1109/iccad.1995.480007openalex-snapshot
Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs
inferredcites →https://doi.org/10.1109/iccad.1997.643251openalex-snapshot
*PHDD: an efficient graph representation for floating point circuit verification
inferredcites →https://doi.org/10.1109/iccd.1995.528918openalex-snapshot
Verification of a subtractive radix-2 square root algorithm and implementation
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot
Verification of arithmetic circuits with binary moment diagrams
inferredcites →https://doi.org/10.1145/240518.240640openalex-snapshot
Word level model checking---avoiding the Pentium FDIV error
inferredcites →https://doi.org/10.21236/ada296684openalex-snapshot
Hybrid Decision Diagrams. Overcoming the Limitations of MTBDDs and BMDs,
inferredcites →https://doi.org/10.5555/224841.224863openalex-snapshot
Efficient construction of binary moment diagrams for verifying arithmetic circuits
inferredcites →https://doi.org/10.5555/266388.266400openalex-snapshot
PHDD: an efficient graph representation for floating point circuit verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-40922-x_1openalex-snapshot
Applications of Hierarchical Verification in Model Checking
inferred← citeshttps://doi.org/10.1007/3-540-44585-4_45openalex-snapshot
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_26openalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_3openalex-snapshot
Applications of Hierarchical Verification in Model Checking
inferred← citeshttps://doi.org/10.1007/3-540-47884-1_11openalex-snapshot
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL
inferred← citeshttps://doi.org/10.1007/978-0-387-35608-2_34openalex-snapshot
Coverage of Implementations by Simulating Specifications
inferred← citeshttps://doi.org/10.1007/978-1-4419-1539-9_3openalex-snapshot
Use of Formal Verification at Centaur Technology
inferred← citeshttps://doi.org/10.1007/978-3-540-39893-6_13openalex-snapshot
Modeling SystemC Fixed-Point Arithmetic in HOL
inferred← citeshttps://doi.org/10.1007/978-3-540-70952-7_1openalex-snapshot
Challenges for Formal Verification in Industrial Setting
inferred← citeshttps://doi.org/10.1007/978-3-642-02658-4_28openalex-snapshot
Centaur Technology Media Unit Verification
inferred← citeshttps://doi.org/10.1007/978-3-642-58322-3_24openalex-snapshot
Proving the Correctness of a Complete Microprocessor
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_38-1openalex-snapshot
Microprocessor Assurance and the Role of Theorem Proving
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_38openalex-snapshot
Microprocessor Assurance and the Role of Theorem Proving
inferred← citeshttps://doi.org/10.1007/s10703-005-1613-yopenalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1007/s10703-005-2256-8openalex-snapshot
Formalization of Fixed-Point Arithmetic in HOL
inferred← citeshttps://doi.org/10.1016/j.ipl.2025.106571openalex-snapshot
Lower bound proof for the size of BDDs representing a shifted addition
inferred← citeshttps://doi.org/10.1093/comjnl/bxp023openalex-snapshot
Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
inferred← citeshttps://doi.org/10.1109/asap.2007.4429962openalex-snapshot
An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder
inferred← citeshttps://doi.org/10.1109/aspdac.2004.1337669openalex-snapshot
Improved symbolic simulation by functional-space decomposition
inferred← citeshttps://doi.org/10.1109/dac.1999.781349openalex-snapshot
Formal verification using parametric representations of Boolean constraints
inferred← citeshttps://doi.org/10.1109/date.2005.75openalex-snapshot
Automatic Formal Verification of Fused-Multiply-Add FPUs
inferred← citeshttps://doi.org/10.1109/fmcad.2015.7542249openalex-snapshot
Universal boolean functional vectors
inferred← citeshttps://doi.org/10.1109/icecs.2006.379845openalex-snapshot
Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification
inferred← citeshttps://doi.org/10.1109/icrc.2017.8123645openalex-snapshot
Still a Fight to Get It Right: Verification in the Era of Machine Learning
inferred← citeshttps://doi.org/10.1109/spl.2012.6211776openalex-snapshot
Generic construction of monitors for Floating Point Unit designs
inferred← citeshttps://doi.org/10.1109/spl.2014.7002208openalex-snapshot
Components for Coverage-Driven Verification of floating-point units
inferred← citeshttps://doi.org/10.1109/tcad.2005.850814openalex-snapshot
An industrially effective environment for formal hardware verification
inferred← citeshttps://doi.org/10.1109/test.2000.894219openalex-snapshot
Static property checking using ATPG vs. BDD techniques
inferred← citeshttps://doi.org/10.1145/309847.309968openalex-snapshot
Formal verification using parametric representations of Boolean constraints
inferred← citeshttps://doi.org/10.22028/d291-25704openalex-snapshot
Formal verification of a fully IEEE compliant floating point unit
inferred← citeshttps://doi.org/10.35537/10915/49326openalex-snapshot
Contribuciones a la verificación funcional moderna
inferred← citeshttps://doi.org/10.4204/eptcs.70.7openalex-snapshot
Bit-Blasting ACL2 Theorems
inferred← citeshttps://doi.org/10.5555/1015090.1015263openalex-snapshot
Improved symbolic simulation by functional-space decomposition
inferred← citeshttps://doi.org/10.5555/1998496.1998525openalex-snapshot
Automatic verification of estimate functions with polynomials of bounded functions
inferred← citeshttps://doi.org/10.5555/968878.969004openalex-snapshot
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
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