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ACL2 theorems about commercial microprocessors

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/j.1538-7305.1990.tb00102.xopenalex-snapshot
Software for Analytical Development of Communications Protocols
inferredcites →https://doi.org/10.1007/3-540-58179-0_44openalex-snapshot
Automatic verification of pipelined microprocessor control
inferredcites →https://doi.org/10.1007/3-540-60385-9_2openalex-snapshot
Automatic verification of the SCI cache coherence protocol
inferredcites →https://doi.org/10.1007/3-540-61474-5_62openalex-snapshot
Verifying the SRT division algorithm using theorem proving techniques
inferredcites →https://doi.org/10.1007/3-540-61474-5_63openalex-snapshot
Modular verification of SRT division
inferredcites →https://doi.org/10.1007/978-0-585-33654-1openalex-snapshot
Piton: A Mechanically Verified Assembly-Level Language
inferredcites →https://doi.org/10.1007/978-94-009-1675-3_6openalex-snapshot
Interaction with the Boyer—Moore Theorem Prover: A Tutorial Study Using the Arithmetic—Geometric Mean Theorem
inferredcites →https://doi.org/10.1007/bf00243132openalex-snapshot
Microprocessor design verification
inferredcites →https://doi.org/10.1007/bf00244463openalex-snapshot
Interaction with the Boyer-Moore theorem prover: A tutorial study using the arithmetic-geometric mean theorem
inferredcites →https://doi.org/10.1007/bf01383968openalex-snapshot
Verification of the Futurebus+ cache coherence protocol
inferredcites →https://doi.org/10.1007/bf01384049openalex-snapshot
Gordon's computer: A hardware verification case study in OBJ3
inferredcites →https://doi.org/10.1016/0378-4754(89)90181-xopenalex-snapshot
A computational logic handbook
inferredcites →https://doi.org/10.1016/c2013-0-10412-6openalex-snapshot
A Computational Logic Handbook
inferredcites →https://doi.org/10.1098/rsta.1992.0024openalex-snapshot
A formal HDL and its use in the FM9001 verification
inferredcites →https://doi.org/10.1109/43.275352openalex-snapshot
Symbolic model checking for sequential circuit verification
inferredcites →https://doi.org/10.1109/52.57892openalex-snapshot
Formal verification of a pipelined microprocessor
inferredcites →https://doi.org/10.1109/cmpass.1996.507872openalex-snapshot
ACL2: an industrial strength version of Nqthm
inferredcites →https://doi.org/10.1109/wift.1995.515475openalex-snapshot
Formal verification of the AAMP5 microprocessor: a case study in the industrial use of formal methods
inferredcites →https://doi.org/10.1117/12.190874openalex-snapshot
Architecture of a complex arithmetic processor for communication signal processing
inferredcites →https://doi.org/10.1145/217474.217583openalex-snapshot
Verification of arithmetic circuits with binary moment diagrams
inferredcites →https://doi.org/10.1145/227595.227603openalex-snapshot
Automated proofs of object code for a widely used microprocessor
inferredcites →https://doi.org/10.1145/240518.240643openalex-snapshot
Bit-level analysis of an SRT divider circuit
inferredcites →https://doi.org/10.21236/ada281028openalex-snapshot
Verification of Arithmetic Functions with Binary Moment Diagrams
inferredcites →https://doi.org/10.5555/224841.224875openalex-snapshot
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What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Formal Reasoning About a Specification-Based Intrusion Detection for Dynamic Auto-configuration Protocols in Ad Hoc Networks
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Refinement and Theorem Proving
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Correctness of Pipelined Machines
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Introduction
inferred← citeshttps://doi.org/10.1007/978-1-4419-5998-0_3openalex-snapshot
Introduction to ACL2
inferred← citeshttps://doi.org/10.1007/978-1-4615-1567-8_23openalex-snapshot
Towards a Mechanically Checked Theory of Computation
inferred← citeshttps://doi.org/10.1007/978-1-4757-3326-6_23openalex-snapshot
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Industrial Deployment of Formal Methods: Trends and Challenges
inferred← citeshttps://doi.org/10.1007/978-3-642-39634-2_31openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-57199-2_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-59615-5_2openalex-snapshot
General Purpose Theorem Proving Methods in the Verification of Digital Hardware and Software
inferred← citeshttps://doi.org/10.1007/bfb0000475openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0028728openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0028729openalex-snapshot
Transforming the theorem prover into a digital design tool: From concept car to off-road vehicle
inferred← citeshttps://doi.org/10.1007/bfb0028769openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/bfb0054262openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/pl00010806openalex-snapshot
Theorem proving in technology transfer: the user’s point of view
inferred← citeshttps://doi.org/10.1007/pl00010807openalex-snapshot
Verification of Year 2000 conversion rules using the ACL2 theorem prover
inferred← citeshttps://doi.org/10.1007/s10009-014-0306-5openalex-snapshot
Expressive program verification via structured specifications
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Ordinal Arithmetic: Algorithms and Mechanization
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Proving Fairness and Implementation Correctness of a Microkernel Scheduler
inferred← citeshttps://doi.org/10.1007/s10817-009-9140-yopenalex-snapshot
A Formalization of Powerlist Algebra in ACL2
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Verifying safety critical task scheduling systems in PPTL axiom system
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Automated Conjecturing and Theorem Finding: A Survey
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Design-time formal verification for smart environments: an exploratory perspective
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A Mechanically Checked Proof of a Multiprocessor Result via a Uniprocessor View
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Floating Point Verification in HOL Light: The Exponential Function
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Nonstandard Analysis in ACL2
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The Correctness of the Fast Fourier Transform: A Structured Proof in ACL2
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Structured Theory Development for a Mechanized Logic
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Partial Functions in ACL2
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Industrial hardware and software verification with ACL2
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A mechanically checked proof of the AMD5/sub K/86/sup TM/ floating-point division program
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An industrial strength theorem prover for a logic based on Common Lisp
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Verifying the FM9801 microarchitecture
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An efficient graph representation for arithmetic circuit verification
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Formal modelling of the ADSP-2100 processor using HOL
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Complementary Formal Approaches for Dependability Analysis
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Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core
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