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Data flow and dependence analysis for instruction level parallelism

https://doi.org/10.1007/bfb0038668
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-06859-7_145openalex-snapshot
First version of a data flow procedure language
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/2.19820openalex-snapshot
The Cydra 5 departmental supercomputer: design philosophies, decisions, and trade-offs
inferredcites →https://doi.org/10.1109/mc.1982.1653940openalex-snapshot
The U-Interpreter
inferredcites →https://doi.org/10.1145/1468075.1468134openalex-snapshot
A language design for concurrent processes
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/36204.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/75277.75280openalex-snapshot
An efficient method of computing static single assignment form
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/99583.99595openalex-snapshot
Dependence flow graphs: an algebraic approach to program dependencies

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44905-1_6openalex-snapshot
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling
inferred← citeshttps://doi.org/10.1007/3-540-55984-1_18openalex-snapshot
Register pipelining: An integrated approach to register allocation for scalar and subscripted variables
inferred← citeshttps://doi.org/10.1007/3-540-57659-2_24openalex-snapshot
Acceleration of first and higher order recurrences on processors with instruction level parallelism
inferred← citeshttps://doi.org/10.1007/978-0-387-09766-4_65openalex-snapshot
Modulo Scheduling and Loop Pipelining
inferred← citeshttps://doi.org/10.1007/978-1-4615-3200-2_3openalex-snapshot
Instruction-Level Parallel Processing: History, Overview, and Perspective
inferred← citeshttps://doi.org/10.1007/978-1-4615-3200-2_6openalex-snapshot
Compiling for the Cydra 5
inferred← citeshttps://doi.org/10.1007/978-1-4899-7797-7_6openalex-snapshot
Modulo Scheduling
inferred← citeshttps://doi.org/10.1007/bf01205181openalex-snapshot
Instruction-level parallel processing: History, overview, and perspective
inferred← citeshttps://doi.org/10.1007/bf01205184openalex-snapshot
Compiling for the Cydra
inferred← citeshttps://doi.org/10.1007/bf03356742openalex-snapshot
Iterative Modulo Scheduling
inferred← citeshttps://doi.org/10.1007/bf03356743openalex-snapshot
Parallelization of Control Recurrences for ILP Processors
inferred← citeshttps://doi.org/10.1007/bf03356757openalex-snapshot
Array Data Flow Analysis for Load-Store Optimizations in Fine-Grain Architectures
inferred← citeshttps://doi.org/10.1007/bfb0024782openalex-snapshot
Génération de micro-code parallèle pour la carte coprocesseur Rapid-2
inferred← citeshttps://doi.org/10.1016/s0020-0255(96)00273-3openalex-snapshot
The complexity of scheduling for data cache optimization
inferred← citeshttps://doi.org/10.1023/a:1008842521805openalex-snapshot
Machine-Description Driven Compilers for EPIC and VLIW Processors
inferred← citeshttps://doi.org/10.1023/a:1018733528538openalex-snapshot
Design Alternatives of Multithreaded Architecture
inferred← citeshttps://doi.org/10.1109/40.888704openalex-snapshot
An advanced optimizer for the IA-64 architecture
inferred← citeshttps://doi.org/10.1109/5.964445openalex-snapshot
Compiling for EPIC architectures
inferred← citeshttps://doi.org/10.1109/micro.1994.717409openalex-snapshot
Height reduction of control recurrences for ILP processors
inferred← citeshttps://doi.org/10.1109/micro.1994.717412openalex-snapshot
Iterative module scheduling: an algorithm for software pipelining loops
inferred← citeshttps://doi.org/10.1109/micro.1994.717426openalex-snapshot
Dynamic memory disambiguation for array references
inferred← citeshttps://doi.org/10.1109/micro.1995.476842openalex-snapshot
Unrolling-based optimizations for modulo scheduling
inferred← citeshttps://doi.org/10.1109/pact.2007.4336200openalex-snapshot
Rotating Register Allocation for Enhanced Pipeline Scheduling
inferred← citeshttps://doi.org/10.1109/tc.2002.1032620openalex-snapshot
Unroll-based copy elimination for enhanced pipeline scheduling
inferred← citeshttps://doi.org/10.1145/143095.143141openalex-snapshot
Register allocation for software pipelined loops
inferred← citeshttps://doi.org/10.1145/1542452.1542454openalex-snapshot
Modulo scheduling without overlapped lifetimes
inferred← citeshttps://doi.org/10.1145/155090.155097openalex-snapshot
A practical data flow framework for array reference analysis and its use in optimizations
inferred← citeshttps://doi.org/10.1145/155090.155115openalex-snapshot
Lifetime-sensitive modulo scheduling
inferred← citeshttps://doi.org/10.1145/192724.192729openalex-snapshot
Height reduction of control recurrences for ILP processors
inferred← citeshttps://doi.org/10.1145/192724.192731openalex-snapshot
Iterative modulo scheduling
inferred← citeshttps://doi.org/10.1145/192724.192737openalex-snapshot
Dynamic memory disambiguation for array references
inferred← citeshttps://doi.org/10.1145/197320.197366openalex-snapshot
Improving the ratio of memory operations to floating-point operations in loops
inferred← citeshttps://doi.org/10.1145/268946.268966openalex-snapshot
Path-sensitive value-flow analysis
inferred← citeshttps://doi.org/10.1145/2847263.2847282openalex-snapshot
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3192366.3192393openalex-snapshot
SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores
inferred← citeshttps://doi.org/10.1145/335231.335260openalex-snapshot
Unroll-based register coalescing
inferred← citeshttps://doi.org/10.1145/502217.502243openalex-snapshot
ShiftQ
inferred← citeshttps://doi.org/10.3390/rs61010107openalex-snapshot
Graph-Based Divide and Conquer Method for Parallelizing Spatial Operations on Vector Data
inferred← citeshttps://doi.org/10.3929/ethz-a-001436167openalex-snapshot
Optimizing compilers for structured programming languages
inferred← citeshttps://doi.org/10.5555/225160.225209openalex-snapshot
Unrolling-based optimizations for modulo scheduling
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93300openalex-snapshot
Binary Redundancy Elimination
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93313openalex-snapshot
Loop pipelining with resource and timing constraints
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