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Delay-insensitive circuits: An algebraic approach to their design

https://doi.org/10.1007/bfb0039070
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-15670-4_14openalex-snapshot
An improved failures model for communicating processes
inferredcites →https://doi.org/10.1007/3-540-51305-1_10openalex-snapshot
Networks of communicating processes and their (De-)composition
inferredcites →https://doi.org/10.1007/978-3-642-82921-5_4openalex-snapshot
Notes on Communicating Sequential Systems
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1007/bfb0023748openalex-snapshot
An algebra for delay-insensitive circuits
inferredcites →https://doi.org/10.1016/0304-3975(88)90049-7openalex-snapshot
The laws of OCCAM programming
inferredcites →https://doi.org/10.1049/ip-e:19860034openalex-snapshot
Automatic verification of asynchronous circuits using temporal logic
inferredcites →https://doi.org/10.1145/63526.63532openalex-snapshot
Micropipelines
inferredcites →https://doi.org/10.6100/ir25052openalex-snapshot
Classification and composition of delay-insensitive circuits
inferredcites →https://doi.org/10.6100/ir272918openalex-snapshot
Translating programs into delay-insensitive circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
inferredcites →https://doi.org/10.7907/zmy86-a1w29openalex-snapshot
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.587openalex-snapshot
Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1
inferred← citeshttps://doi.org/10.1006/jpdc.2001.1806openalex-snapshot
Distributed Simulation of Asynchronous Hardware: The Program Driven Synchronization Protocol
inferred← citeshttps://doi.org/10.1007/3-540-53982-4_19openalex-snapshot
A calculus of broadcasting systems
inferred← citeshttps://doi.org/10.1007/978-0-387-35311-1_22openalex-snapshot
Multi-View Design of Asynchronous Micropipeline Systems using Rainbow
inferred← citeshttps://doi.org/10.1007/978-1-4471-3575-3_2openalex-snapshot
Parallel Program and Asynchronous Circuit Design
inferred← citeshttps://doi.org/10.1007/978-1-4471-3756-6_20openalex-snapshot
Timed Process Algebra, Petri Nets, and Event Refinement
inferred← citeshttps://doi.org/10.1007/978-3-642-38164-5_5openalex-snapshot
Diagrammatic Reasoning for Delay-Insensitive Asynchronous Circuits
inferred← citeshttps://doi.org/10.1007/bf01178564openalex-snapshot
Receptive process theory
inferred← citeshttps://doi.org/10.1007/bf01384074openalex-snapshot
Design and analysis of delay-insensitive modulo-N counters
inferred← citeshttps://doi.org/10.1007/bfb0054293openalex-snapshot
Formal derivation of a loadable asynchronous counter
inferred← citeshttps://doi.org/10.1016/0167-6423(95)00017-8openalex-snapshot
A calculus of broadcasting systems
inferred← citeshttps://doi.org/10.1016/s0928-4869(00)00005-7openalex-snapshot
Modelling and distributed simulation of asynchronous hardware
inferred← citeshttps://doi.org/10.1109/async.1994.656313openalex-snapshot
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra
inferred← citeshttps://doi.org/10.1109/async.1998.666503openalex-snapshot
Analyzing specifications for delay-insensitive circuits
inferred← citeshttps://doi.org/10.1109/csd.2004.1309119openalex-snapshot
Verification and implementation of delay-insensitive processes in restrictive environments
inferred← citeshttps://doi.org/10.1109/eurmic.1997.617282openalex-snapshot
Occam: an asynchronous hardware description language?
inferred← citeshttps://doi.org/10.1109/hicss.1993.270634openalex-snapshot
A verifier for network decompositions of command-based specifications
inferred← citeshttps://doi.org/10.1109/simsym.2004.1299484openalex-snapshot
Modelling SMIPS: a synthesisable asynchronous MIPS processor
inferred← citeshttps://doi.org/10.1177/0037549703038884openalex-snapshot
Modeling an Asynchronous Microprocessor
inferred← citeshttps://doi.org/10.5555/987679.987697openalex-snapshot
Modelling SAMIPS: a synthesisable asynchronous MIPS processor
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