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Hardware cache optimization for parallel multimedia applications

https://doi.org/10.1007/bfb0057949
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-61626-8_53openalex-snapshot
A unified transformation technique for multilevel blocking
inferredcites →https://doi.org/10.1007/978-1-4757-2358-8openalex-snapshot
Image and Video Compression Standards
inferredcites →https://doi.org/10.1007/bf01130407openalex-snapshot
Instruction level power analysis and optimization of software
inferredcites →https://doi.org/10.1007/bfb0024705openalex-snapshot
System-level memory management for weakly parallel image processing
inferredcites →https://doi.org/10.1016/b978-044482106-5/50016-8openalex-snapshot
A Highly Parallel Single Chip Video signal Processor
inferredcites →https://doi.org/10.1016/s0167-8191(97)00083-5openalex-snapshot
Parallel processing and multimedia
inferredcites →https://doi.org/10.1016/s0167-8191(97)00089-6openalex-snapshot
Memory size reduction through storage order optimization for embedded parallel multimedia applications
inferredcites →https://doi.org/10.1109/71.97902openalex-snapshot
A loop transformation theory and an algorithm to maximize parallelism
inferredcites →https://doi.org/10.1109/76.728414openalex-snapshot
Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems
inferredcites →https://doi.org/10.1109/ipps.1998.669928openalex-snapshot
Code transformations for low power caching in embedded multimedia processors
inferredcites →https://doi.org/10.1109/isscc.1997.585250openalex-snapshot
The network computer and its future
inferredcites →https://doi.org/10.1109/isss.1996.565886openalex-snapshot
Memory organization for improved data cache performance in embedded processors
inferredcites →https://doi.org/10.1109/mtdt.1995.518086openalex-snapshot
Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/106974.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/209936.209954openalex-snapshot
Data and computation transformations for multiprocessors
inferredcites →https://doi.org/10.1145/224081.224090openalex-snapshot
Energy optimization of multi-level processor cache architectures
inferredcites →https://doi.org/10.1145/263272.263278openalex-snapshot
Formalized methodology for data reuse exploration in hierarchical memory mappings
inferredcites →https://doi.org/10.1145/263272.263310openalex-snapshot
Analytical energy dissipation models for low-power caches
inferredcites →https://doi.org/10.1145/263272.263342openalex-snapshot
Analysis of power consumption in memory hierarchies
inferredcites →https://doi.org/10.1145/268424.268464openalex-snapshot
Memory data organization for improved cache performance in embedded processor applications
inferredcites →https://doi.org/10.5555/524431.857916openalex-snapshot
Memory organization for improved data cache performance in embedded processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-48311-x_94openalex-snapshot
Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications
inferred← citeshttps://doi.org/10.1007/s11042-006-6145-yopenalex-snapshot
Cache modeling and optimization for portable devices running MPEG-4 video decoder
inferred← citeshttps://doi.org/10.1007/s11554-008-0082-0openalex-snapshot
Custom parallel caching schemes for hardware-accelerated image compression
inferred← citeshttps://doi.org/10.1023/a:1022340119745openalex-snapshot
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications
inferred← citeshttps://doi.org/10.1023/b:vlsi.0000017003.70829.34openalex-snapshot
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors
inferred← citeshttps://doi.org/10.1109/aiccsa.2006.205161openalex-snapshot
Cache Optimization for Embedded Systems Running H.264/AVC Video Decoder
inferred← citeshttps://doi.org/10.1109/cccm.2009.5267937openalex-snapshot
Cache optimization for real time MPEG-4 encoder
inferred← citeshttps://doi.org/10.1109/date.2000.840306openalex-snapshot
How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level?
inferred← citeshttps://doi.org/10.1109/icecs.2001.957735openalex-snapshot
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures
inferred← citeshttps://doi.org/10.1109/icosp.2006.345501openalex-snapshot
Cache optimization for an embedded MPEG-4 video decoder
inferred← citeshttps://doi.org/10.1109/mmse.2004.34openalex-snapshot
Cache Optimization for Mobile Devices Running Multimedia Applications
inferred← citeshttps://doi.org/10.1109/secon.2009.5174113openalex-snapshot
Performance and energy consumption optimization by tuning level-2 cache attributes for real-time signal processing systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2002.800530openalex-snapshot
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors
inferred← citeshttps://doi.org/10.1145/343647.343813openalex-snapshot
How to solve the current memory access and data transfer bottlenecks
inferred← citeshttps://doi.org/10.1145/500001.500027openalex-snapshot
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications
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