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On predicting data cache behavior for real-time systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-18991-2_14openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1007/3-540-60360-3_31openalex-snapshot
Generation of efficient interprocedural analyzers with PAG
inferredcites →https://doi.org/10.1007/3-540-61739-6_33openalex-snapshot
Cache behavior prediction by abstract interpretation
inferredcites →https://doi.org/10.1007/bfb0057777openalex-snapshot
On predicting data cache behavior for real-time systems
inferredcites →https://doi.org/10.1016/0743-7315(88)90014-7openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1016/s0167-6423(99)00010-6openalex-snapshot
Cache behavior prediction by abstract interpretation
inferredcites →https://doi.org/10.1109/2.76286openalex-snapshot
Experiments with a program timing tool based on source-level timing schema
inferredcites →https://doi.org/10.1109/32.392980openalex-snapshot
An accurate worst case timing analysis for RISC processors
inferredcites →https://doi.org/10.1109/71.97902openalex-snapshot
A loop transformation theory and an algorithm to maximize parallelism
inferredcites →https://doi.org/10.1109/emwrts.1997.613765openalex-snapshot
Generalizing timing predictions to set-associative caches
inferredcites →https://doi.org/10.1109/real.1994.342717openalex-snapshot
Deterministic upperbounds of the worst-case execution times of cached programs
inferredcites →https://doi.org/10.1109/real.1995.495219openalex-snapshot
Efficient microarchitecture modeling and path analysis for real-time software
inferredcites →https://doi.org/10.1109/real.1995.495220openalex-snapshot
Worst case timing analysis of RISC processors: R3000/R3010 case study
inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot
Cache modeling for real-time software: beyond direct mapped instruction caches
inferredcites →https://doi.org/10.1109/rttas.1996.509540openalex-snapshot
Efficient worst case timing analysis of data caching
inferredcites →https://doi.org/10.1109/rttas.1997.601358openalex-snapshot
Timing analysis for data caches and set-associative caches
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/2591635.2667155openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1145/3392717.3400034openalex-snapshot
Optimizing supercompilers for supercomputers
inferredcites →https://doi.org/10.22028/d291-25822openalex-snapshot
A fast and efficient cache persistence analysis
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Applying Abstract Interpretation to Demonstrate Functional Safety
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Worst‐case execution time analysis‐driven object cache design
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Verifying Timing Behavior by Abstract Interpretation of Executable Code
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Analyzing the Worst-Case Execution Time by Abstract Interpretation of Executable Code
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Optimized Live Heap Bound Analysis
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PROPAN: A Retargetable System for Postpass Optimisations and Analyses
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Reliable and Precise WCET Determination for a Real-Life Processor
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Pipeline Modeling for Timing Analysis
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ILP-Based Interprocedural Path Analysis
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Bottom-Up Performance Analysis of HW/SW Platforms
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A Journey of Embedded and Cyber-Physical Systems : Essays Dedicated to Peter Marwedel on the Occasion of His 70th Birthday
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Testing Implementation Soundness of a WCET Analysis Tool
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Proving the Absence of Stack Overflows
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MRU Cache Analysis for WCET Estimation
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FIFO Cache Analysis for WCET Estimation
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Analyzing Preemptive Global Scheduling
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Analyzing Non-preemptive Global Scheduling
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Parametric Utilization Bounds
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Why AI + ILP Is Good for WCET, but MC Is Not, Nor ILP Alone
inferred← citeshttps://doi.org/10.1007/978-3-540-30476-0_20openalex-snapshot
Component-Wise Instruction-Cache Behavior Prediction
inferred← citeshttps://doi.org/10.1007/978-3-540-70545-1_6openalex-snapshot
Abstract Interpretation with Applications to Timing Validation
inferred← citeshttps://doi.org/10.1007/978-3-540-70930-5_10openalex-snapshot
Towards Model-Driven Development of Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1007/978-3-540-71322-7_1openalex-snapshot
An Appreciation of the Work of Reinhard Wilhelm
inferred← citeshttps://doi.org/10.1007/978-3-540-71322-7_2openalex-snapshot
New Developments in WCET Analysis
inferred← citeshttps://doi.org/10.1007/978-3-642-03237-0_10openalex-snapshot
Abstract Interpretation of FIFO Replacement
inferred← citeshttps://doi.org/10.1007/978-3-642-10265-3_17openalex-snapshot
Towards Time-Predictable Data Caches for Chip-Multiprocessors
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100% Coverage for Safety-Critical Software – Efficient Testing by Static Analysis
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McAiT – A Timing Analyzer for Multicore Real-Time Software
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Run-Time Guarantees for Real-Time Systems—The USES Approach
inferred← citeshttps://doi.org/10.1007/bfb0057786openalex-snapshot
Cache sensitive pre-runtime scheduling
inferred← citeshttps://doi.org/10.1007/s10009-012-0248-8openalex-snapshot
Architecture exploration and timing estimation during early design phases
inferred← citeshttps://doi.org/10.1007/s11241-014-9212-xopenalex-snapshot
Static probabilistic worst case execution time estimation for architectures with faulty instruction caches
inferred← citeshttps://doi.org/10.1007/s11241-018-9305-zopenalex-snapshot
Response-time analysis for fixed-priority systems with a write-back cache
inferred← citeshttps://doi.org/10.1016/j.scico.2015.06.006openalex-snapshot
Certifying execution time in multicores
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.08.007openalex-snapshot
WCET analysis of instruction cache hierarchies
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.04.001openalex-snapshot
Scope-aware data cache analysis for OpenMP programs on multi-core processors
inferred← citeshttps://doi.org/10.1016/s1383-7621(00)00053-9openalex-snapshot
Execution cost interval refinement in static software analysis
inferred← citeshttps://doi.org/10.1023/a:1008138407139openalex-snapshot
An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution
inferred← citeshttps://doi.org/10.1023/a:1008141130870openalex-snapshot
Fast and Precise WCET Prediction by Separated Cache and Path Analyses
inferred← citeshttps://doi.org/10.1023/a:1008186323068openalex-snapshot
Efficient and Precise Cache Behavior Prediction for Real-Time Systems
inferred← citeshttps://doi.org/10.1023/a:1019734423460openalex-snapshot
Hybrid Cache Analysis in Running Time Verification of Embedded Software
inferred← citeshttps://doi.org/10.1109/aspdac.2007.358018openalex-snapshot
A Retargetable Software Timing Analyzer Using Architecture Description Language
inferred← citeshttps://doi.org/10.1109/dac.2002.1012637openalex-snapshot
Model composition for scheduling analysis in platform design
inferred← citeshttps://doi.org/10.1109/date.2002.998348openalex-snapshot
Event model interfaces for heterogeneous system analysis
inferred← citeshttps://doi.org/10.1109/ecrts.2010.21openalex-snapshot
Investigating Average versus Worst-Case Timing Behavior of Data Caches and Data Scratchpads
inferred← citeshttps://doi.org/10.1109/ecrts.2014.16openalex-snapshot
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques
inferred← citeshttps://doi.org/10.1109/embeddedcom-scalcom.2009.16openalex-snapshot
Multi-core and VMM Based Non-interference Test Method of Embedded System Software
inferred← citeshttps://doi.org/10.1109/hldvt.2000.889577openalex-snapshot
Data flow based cache prediction using local simulation
inferred← citeshttps://doi.org/10.1109/ictc55196.2022.9952775openalex-snapshot
Towards Access Pattern Prediction for Big Data Applications
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Case study: Performance and WCET analysis for parallelised avionic applications with ODC2
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Intervals in software execution cost analysis
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Interdependent cache analyses for better precision and safety
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Experimental evaluation of code properties for WCET analysis
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Scope-Aware Data Cache Analysis for WCET Estimation
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Providing task isolation via TLB coloring
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Precise Cache Timing Analysis via Symbolic Execution
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Scope-Aware Useful Cache Block Analysis for Data Cache Related Preemption Delay
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A method to improve the estimated worst-case performance of data caching
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Making worst case execution time analysis for hard real-time tasks on state of the art processors feasible
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Bounding the execution time of real-time tasks on modern processors
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Unified Cache Modeling for WCET Analysis and Layout Optimizations
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Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems
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Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time
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An overview of embedded system design education at berkeley
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WCET estimation for executables in the presence of data caches
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Exploiting stack distance to estimate worst-case data cache performance
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Parametric heap usage analysis for functional programs
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Probabilistic modeling of data cache behavior
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WCET driven design space exploration of an object cache
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Shared hardware data structures for hard real-time systems
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Static probabilistic worst case execution time estimation for architectures with faulty instruction caches
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Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems
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Improving the Precision of Abstract Interpretation Based Cache Persistence Analysis
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Handling write backs in multi-level cache analysis for WCET estimation
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Pipeline behavior prediction for superscalar processors by abstract interpretation
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Probabilistic Safe WCET Estimation for Weakly Hard Real-time Systems at Design Stages
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Path-Sensitive Abstract Interpretation for WCET Estimation
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Interval-Based Analysis of Software Processes
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Automatic Accurate Live Memory Analysis for Garbage-Collected Languages
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ILP-based Instruction Scheduling for IA-64
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Model composition for scheduling analysis in platform design
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Worst-Case Execution Time and Energy Analysis
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Reducing WCET Overestimations by Correcting Errors in Loop Bound Constraints
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Probabilistic WCET Estimation in Presence of Hardware for Mitigating the Impact of Permanent Faults
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WCET Analysis of Multi-Level Set-Associative Data Caches
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Static Memory and Execution Time Analysis of Embedded Code
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Towards Integrating Model-Driven Development of Hard Real-Time Systems with Static Program Analyzers
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An Integrated Timing Analysis Methodology for Real-Time Systems
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Eliminating Timing Side-Channel Leaks using Program Repair
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Abstract Interpretation under Speculative Execution
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Renesanční a manýristické štukatérství v Čechách a na Moravě
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Intervals in software execution cost analysis
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Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications
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Bounding Worst-Case Data Cache Performance by Using Stack Distance
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Calcul du pire temps d'exécution : méthode formelle s'adaptant à la sophistication croissante des architectures matérielles
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