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Improving Dependability and Performance of Fully Asynchronous On-chip Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0167-9260(93)90036-copenalex-snapshot
The Post Office experience: designing a large asynchronous chip
inferredcites →https://doi.org/10.1049/el.2010.0634openalex-snapshot
Monitoring circuit based on threshold for fault-tolerant NoC
inferredcites →https://doi.org/10.1049/ip-cdt:20000187openalex-snapshot
Fault-tolerant wormhole routing algorithm for mesh networks
inferredcites →https://doi.org/10.1109/71.473515openalex-snapshot
A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks
inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
inferredcites →https://doi.org/10.1109/cicc.2007.4405763openalex-snapshot
Reliability Trends with Advanced CMOS Scaling and The Implications for Design
inferredcites →https://doi.org/10.1109/date.2009.5090627openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
inferredcites →https://doi.org/10.1109/ftcs.1993.627327openalex-snapshot
Fault-tolerant wormhole routing in meshes
inferredcites →https://doi.org/10.1109/hpca.2009.4798274openalex-snapshot
Prediction router: Yet another low latency on-chip router architecture
inferredcites →https://doi.org/10.1109/iccd.2001.954997openalex-snapshot
MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines
inferredcites →https://doi.org/10.1109/ipdps.2001.925000openalex-snapshot
Adaptive fault-tolerant wormhole routing in 2D meshes
inferredcites →https://doi.org/10.1109/isscc.2008.4523070openalex-snapshot
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
inferredcites →https://doi.org/10.1109/isvlsi.2007.85openalex-snapshot
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs
inferredcites →https://doi.org/10.1109/jssc.2007.910957openalex-snapshot
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
inferredcites →https://doi.org/10.1109/nocs.2010.14openalex-snapshot
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
inferredcites →https://doi.org/10.1109/tcad.2011.2114970openalex-snapshot
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
inferredcites →https://doi.org/10.1109/test.2006.297681openalex-snapshot
Combinational Logic Soft Error Correction
inferredcites →https://doi.org/10.1109/vlsic.2010.5560329openalex-snapshot
A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element
inferredcites →https://doi.org/10.5555/1870926.1870938openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.5555/1874620.1874628openalex-snapshot
A highly resilient routing algorithm for fault-tolerant NoCs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-94583-1_19openalex-snapshot
Scaling Up Livelock Verification for Network-on-Chip Routing Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-319-10702-8_4openalex-snapshot
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip
inferred← citeshttps://doi.org/10.1007/978-4-431-56594-9_19openalex-snapshot
Network-on-Chip Based Multiple-Core Centralized ECUs for Safety-Critical Automotive Applications
inferred← citeshttps://doi.org/10.1007/978-4-431-56594-9_9openalex-snapshot
Responsiveness and Timing
inferred← citeshttps://doi.org/10.1007/s10617-014-9137-6openalex-snapshot
The fast evolving landscape of on-chip communication
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.08.002openalex-snapshot
Variability-tolerant routing algorithms for Networks-on-Chip
inferred← citeshttps://doi.org/10.1016/j.scico.2016.01.002openalex-snapshot
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis
inferred← citeshttps://doi.org/10.1088/1757-899x/925/1/012069openalex-snapshot
Congestion aware Adaptive Reverse Routing Strategy for Improving QoS in WSN
inferred← citeshttps://doi.org/10.1109/apccas.2014.7032872openalex-snapshot
An NoC-based evaluation platform for safety-critical automotive applications
inferred← citeshttps://doi.org/10.1109/aspdac.2014.6742911openalex-snapshot
A low-latency asynchronous interconnection network with early arbitration resolution
inferred← citeshttps://doi.org/10.1109/async.2014.10openalex-snapshot
An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
inferred← citeshttps://doi.org/10.1109/async.2019.00025openalex-snapshot
Hardware Trojan Insertion and Detection in Asynchronous Circuits
inferred← citeshttps://doi.org/10.1109/ddecs.2015.30openalex-snapshot
NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/dft.2011.38openalex-snapshot
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
inferred← citeshttps://doi.org/10.1109/dft.2012.6378227openalex-snapshot
Dependable routing in multi-chip NoC platforms for automotive applications
inferred← citeshttps://doi.org/10.1109/dsd.2013.40openalex-snapshot
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip
inferred← citeshttps://doi.org/10.1109/dsd.2016.71openalex-snapshot
Fault Tolerant Deadlock-Free Adaptive Routing Algorithms for Hexagonal Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357132openalex-snapshot
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits
inferred← citeshttps://doi.org/10.1109/iscas.2014.6865085openalex-snapshot
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits
inferred← citeshttps://doi.org/10.1109/prdc.2012.18openalex-snapshot
Performance Modeling and Analysis of On-chip Networks for Real-Time Applications
inferred← citeshttps://doi.org/10.1109/prdc.2012.20openalex-snapshot
Multi-chip NoCs for Automotive Applications
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2729081openalex-snapshot
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2014.7004164openalex-snapshot
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
inferred← citeshttps://doi.org/10.1145/2591513.2591518openalex-snapshot
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip
inferred← citeshttps://doi.org/10.1145/2744769.2744777openalex-snapshot
A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's
inferred← citeshttps://doi.org/10.1145/3822454.3822495openalex-snapshot
Cross-Layer Analysis of Permanent Faults in Asynchronous NoCs for Neuromorphic Computing
inferred← citeshttps://doi.org/10.11591/ijeecs.v33.i2.pp777-786openalex-snapshot
Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip
inferred← citeshttps://doi.org/10.1587/transfun.e98.a.1519openalex-snapshot
Novel Implementation Method of Multiple-Way Asynchronous Arbiters
inferred← citeshttps://doi.org/10.1587/transinf.e96.d.1914openalex-snapshot
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
inferred← citeshttps://doi.org/10.1587/transinf.e97.d.1546openalex-snapshot
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
inferred← citeshttps://doi.org/10.23919/date.2017.7926959openalex-snapshot
Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach
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