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×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_12openalex-snapshot
xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/43.945302openalex-snapshot
Theory of latency-insensitive design
inferredcites →https://doi.org/10.1109/arvlsi.1999.756051openalex-snapshot
VLSI architecture: past, present, and future
inferredcites →https://doi.org/10.1109/date.2000.840047openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1109/date.2003.1253633openalex-snapshot
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
inferredcites →https://doi.org/10.1109/date.2004.1268966openalex-snapshot
Analyzing on-chip communication in a MPSoC environment
inferredcites →https://doi.org/10.1109/date.2004.1268999openalex-snapshot
×pipesCompiler: a tool for instantiating application specific networks on chip
inferredcites →https://doi.org/10.1109/date.2004.1269002openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.1109/delta.2002.994599openalex-snapshot
Interconnect IP node for future system-on-chip designs
inferredcites →https://doi.org/10.1109/hpca.2003.1183554openalex-snapshot
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
inferredcites →https://doi.org/10.1109/iccd.2003.1240887openalex-snapshot
Efficient synthesis of networks on chip
inferredcites →https://doi.org/10.1109/iccd.2012.6378615openalex-snapshot
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
inferredcites →https://doi.org/10.1109/ipdps.2003.1213180openalex-snapshot
SoCBUS: switched network on chip for hard real time embedded systems
inferredcites →https://doi.org/10.1109/isscc.2002.993087openalex-snapshot
A 0.8 W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback
inferredcites →https://doi.org/10.1109/isscc.2003.1234390openalex-snapshot
An 800MHz star-connected on-chip network for application to systems on a chip
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/pact.2000.888329openalex-snapshot
ASOC: a scalable, single-chip communications architecture
inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot
A generic architecture for on-chip packet-switched interconnections
inferredcites →https://doi.org/10.1145/378239.379046openalex-snapshot
Micronetwork-based integration for SOCs
inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot
On-chip communication architecture for OC-768 network processors
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot
Bandwidth-constrained mapping of cores onto NoC architectures
inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Network Interface Architecture and Design Issues
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Design Methodologies and CAD Tool Flows for NoCs
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A Perspective on Collaboration with Interconnects & Routing in Network on Chip Architectures
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Application-Specific Network-on-Chip synthesis with flexible router Placement
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Mesh 2D Network on Chip with an open core protocol based network interface
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Network Interface Sharing Techniques for Area Optimized NoC Architectures
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Design and implementation of network interface compatible OCP For packet based NOC
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Power minimization for clustered routing in network on chip architectures
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Automatic generation of transducer models for multicore system design
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NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators
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Heterogeneous design methodology with configurable regular topology set for scalable Network-on-Chip designs
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Task model for on-chip communication infrastructure design for multicore systems
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A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip
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A new pipelined network interface for Network on Chip with latency and jitter optimization
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Design of configurable, network based interconnection modules for communication centric System-on-Chip applications
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Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips
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Bringing Network-on-Chip links to 45nm
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Ultra-low latency NoC testing via pseudo-random test pattern compaction
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Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels
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Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems
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Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design
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Synthesis of networks on chips for 3D systems on chips
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Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
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SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
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Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints
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Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline
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Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration
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Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS
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A composable and predictable on-chip interconnect
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An Interconnection Network Topology Generation Scheme for Multicore Systems
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