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Debug of the CELL Processor: Moving the Lab into Silicon
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1023/a:1008307818771openalex-snapshot
Debug Facilities in the TriMedia CPU64 Architecture
inferredcites →https://doi.org/10.1109/43.664230openalex-snapshot
Nonscan design-for-testability techniques using RT-level design information
inferredcites →https://doi.org/10.1109/54.573352openalex-snapshot
Designing UltraSparc for testability
inferredcites →https://doi.org/10.1109/date.2005.109openalex-snapshot
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
inferredcites →https://doi.org/10.1109/etw.1999.804255openalex-snapshot
Debug facilities in the TriMedia CPU64 architecture
inferredcites →https://doi.org/10.1109/ieeestd.2013.6515989openalex-snapshot
IEEE Standard for Test Access Port and Boundary-Scan Architecture
inferredcites →https://doi.org/10.1109/isscc.2005.1493930openalex-snapshot
The design and implementation of a first-generation CELL processor
inferredcites →https://doi.org/10.1109/mdt.1997.573351openalex-snapshot
Microprocessors Lead The Way In Complex Design
inferredcites →https://doi.org/10.1109/mp.2005.1405795openalex-snapshot
An embedding debugging architecture for SOCs
inferredcites →https://doi.org/10.1109/tc.2006.22openalex-snapshot
Debug support strategy for systems-on-chips with multiple processor cores
inferredcites →https://doi.org/10.1109/test.1993.470626openalex-snapshot
Test features of the HP PA7100LC processor
inferredcites →https://doi.org/10.1109/test.1994.527936openalex-snapshot
Testability features of the MC68060 microprocessor
inferredcites →https://doi.org/10.1109/test.1999.805650openalex-snapshot
Logic BIST for large industrial designs: real issues and case studies
inferredcites →https://doi.org/10.1109/test.2000.894198openalex-snapshot
Reducing test data volume using external/LBIST hybrid test patterns
inferredcites →https://doi.org/10.1109/test.2001.966677openalex-snapshot
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
inferredcites →https://doi.org/10.1109/test.2005.1583967openalex-snapshot
Testability features of the first-generation CELL processor
inferredcites →https://doi.org/10.1145/307418.307593openalex-snapshot
On programmable memory built-in self test architectures
inferredcites →https://doi.org/10.13140/rg.2.1.2013.9606openalex-snapshot
The Test Access Port and Boundary-Scan Architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-31424-7_37openalex-snapshot
nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces
inferred← citeshttps://doi.org/10.1007/978-90-481-3282-9_5openalex-snapshot
Generalized Fault Modeling for Logic Diagnosis
inferred← citeshttps://doi.org/10.1007/s10836-009-5109-3openalex-snapshot
Adaptive Debug and Diagnosis Without Fault Dictionaries
inferred← citeshttps://doi.org/10.1109/ats.2014.63openalex-snapshot
An On-Line Timing Error Detection Method for Silicon Debug
inferred← citeshttps://doi.org/10.1109/ets.2007.9openalex-snapshot
Adaptive Debug and Diagnosis without Fault Dictionaries
inferred← citeshttps://doi.org/10.1109/ets.2009.12openalex-snapshot
Speed-Path Debug Using At-Speed Scan Test Patterns
inferred← citeshttps://doi.org/10.1109/fmcad.2008.ecp.9openalex-snapshot
BackSpace: Formal Analysis for Post-Silicon Debug
inferred← citeshttps://doi.org/10.1109/fpl.2014.6927498openalex-snapshot
Effective FPGA debug for high-level synthesis generated circuits
inferred← citeshttps://doi.org/10.1109/fpt.2012.6412102openalex-snapshot
Rapid RTL-based signal ranking for FPGA prototyping
inferred← citeshttps://doi.org/10.1109/isqed.2011.5770739openalex-snapshot
On evaluating signal selection algorithms for post-silicon debug
inferred← citeshttps://doi.org/10.1109/mdat.2017.2691348openalex-snapshot
Post-Silicon Validation in the SoC Era: A Tutorial Introduction
inferred← citeshttps://doi.org/10.1109/mdt.2007.157openalex-snapshot
Cell Broadband Engine Debugging for Unknown Events
inferred← citeshttps://doi.org/10.1109/tcad.2017.2778084openalex-snapshot
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug
inferred← citeshttps://doi.org/10.1109/vldi-dat.2013.6533852openalex-snapshot
Improve speed path identification with suspect path expressions
inferred← citeshttps://doi.org/10.1145/2593069.2593183openalex-snapshot
Post-Silicon Validation of the IBM POWER8 Processor
inferred← citeshttps://doi.org/10.1147/jrd.2014.2380272openalex-snapshot
Debugging post-silicon fails in the IBM POWER8 bring-up lab
inferred← citeshttps://doi.org/10.14288/1.0067636openalex-snapshot
Practical considerations for post-silicon debug using backspace
inferred← citeshttps://doi.org/10.71548/17589openalex-snapshot
ON-CHIP DEBUG ARCHITECTURES FOR IMPROVING OBSERVABILITY DURING POST-SILICON VALIDATION
inferred← citeshttps://doi.org/10.7282/t3rx9cggopenalex-snapshot
SPARTAN: a spectral and entropy-based partial-scan and test point insertion algorithm
inferred← citeshttps://doi.org/10.82308/29621openalex-snapshot
Hardware-based temporal logic checkers for the debugging of digital integrated circuits
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