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Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

https://doi.org/10.1109/fpl.2011.25

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1049/ip-cdt:20050175openalex-snapshot

PNoC: a flexible circuit-switched NoC for FPGA-based systems

inferredcites →https://doi.org/10.1109/40.748793openalex-snapshot

Designing and implementing a fast crossbar scheduler

inferredcites →https://doi.org/10.1109/date.2005.5openalex-snapshot

A Complete Network-On-Chip Emulation Framework

inferredcites →https://doi.org/10.1109/fccm.2006.55openalex-snapshot

Packet Switched vs. Time Multiplexed FPGA Overlay Networks

inferredcites →https://doi.org/10.1109/fpl.2006.311316openalex-snapshot

Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip

inferredcites →https://doi.org/10.1109/fpl.2010.52openalex-snapshot

A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier

inferredcites →https://doi.org/10.1109/fpl.2010.53openalex-snapshot

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers

inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot

A delay model and speculative architecture for pipelined routers

inferredcites →https://doi.org/10.1109/icpp.1996.537144openalex-snapshot

A high performance router architecture for interconnection networks

inferredcites →https://doi.org/10.1109/isca.2005.35openalex-snapshot

Microarchitecture of a High-Radix Router

inferredcites →https://doi.org/10.1109/isvlsi.2007.67openalex-snapshot

MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems

inferredcites →https://doi.org/10.1109/mcas.2007.910029openalex-snapshot

Feature - NoC emulation: a tool and design flow for MPSoC

inferredcites →https://doi.org/10.1109/micro.2008.4771803openalex-snapshot

Token flow control

inferredcites →https://doi.org/10.1109/mm.2007.4378786openalex-snapshot

Challenges and Promising Results in NoC Prototyping Using FPGAs

inferredcites →https://doi.org/10.1109/tcad.2008.2010691openalex-snapshot

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

inferredcites →https://doi.org/10.1109/tvlsi.2007.900746openalex-snapshot

Routability of Network Topologies in FPGAs

inferredcites →https://doi.org/10.1109/vlsid.2007.12openalex-snapshot

A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures

inferredcites →https://doi.org/10.1145/1057661.1057769openalex-snapshot

LiPaR

inferredcites →https://doi.org/10.1145/1080695.1070005openalex-snapshot

Microarchitecture of a High-Radix Router

inferredcites →https://doi.org/10.1145/1117278.1117290openalex-snapshot

The routability of multiprocessor network topologies in FPGAs

inferredcites →https://doi.org/10.1145/1132952.1132953openalex-snapshot

A survey of research and practices of Network-on-chip

inferredcites →https://doi.org/10.1145/1723112.1723118openalex-snapshot

Predicting the performance of application-specific NoCs implemented on FPGAs

inferredcites →https://doi.org/10.2200/s00238ed1v01y200911cac009openalex-snapshot

Introduction to Reconfigurable Supercomputing

inferredcites →https://doi.org/10.5555/1521747.1521786openalex-snapshot

Token flow control

inferredcites →https://doi.org/10.7907/8nfz-4y29openalex-snapshot

Packet-Switched On-Chip FPGA Overlay Networks

inferredcites →https://doi.org/10.7907/wzts-xr26openalex-snapshot

Time-Multiplexed FPGA Overlay Networks on Chip

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4614-1362-2_6openalex-snapshot

Switch Design for Soft Interconnection Networks

inferred← citeshttps://doi.org/10.1007/978-3-319-05960-0_18openalex-snapshot

A Synthesizable Multicore Platform for Microwave Imaging

inferred← citeshttps://doi.org/10.1007/978-3-642-36424-2_7openalex-snapshot

Synthetic Aperture Radar Data Processing on an FPGA Multi-core System

inferred← citeshttps://doi.org/10.1007/978-981-16-2422-3_60openalex-snapshot

Reliable Fault-Tolerance Routing Technique for Network-on-Chip Interconnect

inferred← citeshttps://doi.org/10.1007/s41870-023-01303-wopenalex-snapshot

Controller node derivation for data distribution in Network-on-chip with ring connected binary tree topology

inferred← citeshttps://doi.org/10.1007/s41870-023-01718-5openalex-snapshot

Controller node driven hop count based data distribution algorithm in ring connected binary tree network-on-chip for parallel processing

inferred← citeshttps://doi.org/10.1016/j.micpro.2017.08.007openalex-snapshot

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

inferred← citeshttps://doi.org/10.1109/csnt.2015.111openalex-snapshot

HDL Design for 32 Port Real Time Tera Hertz (Tbps) Wi-Fi Router ASIC Soft IP Core for Complex Network-on-Chip Wireless Internet & Cloud Computing Applications

inferred← citeshttps://doi.org/10.1109/eltech.2018.8401417openalex-snapshot

FPGA-based parallel system for synthetic aperture radar imaging

inferred← citeshttps://doi.org/10.1109/etfa.2012.6489726openalex-snapshot

Shifting SOA to MPSoC: An exploratory example of application

inferred← citeshttps://doi.org/10.1109/fpl.2012.6339135openalex-snapshot

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS

inferred← citeshttps://doi.org/10.1109/hpsr.2015.7483084openalex-snapshot

C-GEP: 100 Gbit/s capable, FPGA-based, reconfigurable networking equipment

inferred← citeshttps://doi.org/10.1109/iccsnt.2015.7490875openalex-snapshot

Design and implementation of the wormhole virtual channel NoC router

inferred← citeshttps://doi.org/10.1109/iscas.2013.6572369openalex-snapshot

FPGA based single cycle, reconfigurable router for NoC applications

inferred← citeshttps://doi.org/10.1109/radecs61970.2024.11298585openalex-snapshot

Assessment of Router Failures Under Proton Beam Radiation

inferred← citeshttps://doi.org/10.1109/reconfig.2011.87openalex-snapshot

The Impact of Global Routing on the Performance of NoCs in FPGAs

inferred← citeshttps://doi.org/10.1109/reconfig.2015.7393323openalex-snapshot

Improving FPGA NoC performance using virtual cut-through switching technique

inferred← citeshttps://doi.org/10.1109/socc.2011.6085089openalex-snapshot

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

inferred← citeshttps://doi.org/10.1109/socc.2012.6398325openalex-snapshot

A power-area analysis of NoCs in FPGAs

inferred← citeshttps://doi.org/10.1109/tcad.2021.3091410openalex-snapshot

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

inferred← citeshttps://doi.org/10.1109/tpds.2014.2360194openalex-snapshot

An Analysis of Hypermesh NoCs in FPGAs

inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2497259openalex-snapshot

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

inferred← citeshttps://doi.org/10.1145/2451636.2451637openalex-snapshot

Reconfigure router design and evaluation for the FPGA-friendly SoCWire network-on-chip

inferred← citeshttps://doi.org/10.1145/3130218.3130238openalex-snapshot

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

inferred← citeshttps://doi.org/10.34218/ijaret.10.2.2019.050openalex-snapshot

FPGA IMPLEMENTATION OF PRIORITY-ARBITER BASED ROUTER DESIGN FOR NOC SYSTEMS

inferred← citeshttps://doi.org/10.4018/978-1-7998-4610-9.ch005openalex-snapshot

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

inferred← citeshttps://doi.org/10.4236/cs.2016.74029openalex-snapshot

Design of Efficient Router with Low Power and Low Latency for Network on Chip

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