On the public citation graph
Vector Lane Threading
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/40.621209openalex-snapshot
Simultaneous multithreading: a platform for next-generation processors
inferredcites →https://doi.org/10.1109/40.918001openalex-snapshot
Imagine: media processing with streams
inferredcites →https://doi.org/10.1109/hpca.1996.501193openalex-snapshot
Decoupled vector architectures
inferredcites →https://doi.org/10.1109/hpca.1997.569677openalex-snapshot
Multithreaded vector architectures
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2004.1310763openalex-snapshot
The vector-thread architecture
inferredcites →https://doi.org/10.1109/isscc.2002.992247openalex-snapshot
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
inferredcites →https://doi.org/10.1109/isscc.2002.993068openalex-snapshot
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
inferredcites →https://doi.org/10.1109/isscc.2005.1493930openalex-snapshot
The design and implementation of a first-generation CELL processor
inferredcites →https://doi.org/10.1109/micro.1997.645807openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.1109/micro.2002.1176257openalex-snapshot
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/sc.2002.10053openalex-snapshot
A 26.58 Tflops Global Atmospheric Simulation with the Spectral Transform Method on the Earth Simulator
inferredcites →https://doi.org/10.1109/sc.2004.54openalex-snapshot
Scientific Computations on Modern Parallel Vector Systems
inferredcites →https://doi.org/10.1145/1028176.1006736openalex-snapshot
The Vector-Thread Architecture
inferredcites →https://doi.org/10.1145/1048935.1050169openalex-snapshot
Early Evaluation of the Cray X1
inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/305138.305148openalex-snapshot
Adding a vector unit to a superscalar processor
inferredcites →https://doi.org/10.1177/109434208900300302openalex-snapshot
The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers
inferredcites →https://doi.org/10.5555/266800.266816openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.5555/762761.762828openalex-snapshot
A 26.58 Tflops Global Atmospheric Simulation with the Spectral Transform Method on the Earth Simulator
inferredcites →https://doi.org/10.5555/774861.774892openalex-snapshot
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s42514-020-00057-2openalex-snapshot
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions
inferred← citeshttps://doi.org/10.1016/j.mejo.2015.03.012openalex-snapshot
Merging VLIW and vector processing techniques for a simple, high-performance processor architecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.12.001openalex-snapshot
SIMD stealing: Architectural support for efficient data parallel execution on multicores
inferred← citeshttps://doi.org/10.1109/asap.2008.4580154openalex-snapshot
Run-time thread sorting to expose data-level parallelism
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522353openalex-snapshot
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00063openalex-snapshot
A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00063openalex-snapshot
Adaptable Register File Organization for Vector Processors
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00061openalex-snapshot
VSA: A Hybrid Vector-Systolic Architecture
inferred← citeshttps://doi.org/10.1109/icces.2014.7030959openalex-snapshot
FPGA implementation and performance evaluation of a simultaneous multithreaded matrix processor
inferred← citeshttps://doi.org/10.1109/icde65448.2025.00274openalex-snapshot
Optimizing Queries with Many-to-Many Joins
inferred← citeshttps://doi.org/10.1109/ipdps.2012.20openalex-snapshot
Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth
inferred← citeshttps://doi.org/10.1109/isca.2012.6237005openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00049openalex-snapshot
Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00025openalex-snapshot
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
inferred← citeshttps://doi.org/10.1109/tc.2013.2295820openalex-snapshot
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores
inferred← citeshttps://doi.org/10.1109/vldi-dat.2013.6533822openalex-snapshot
A distributed thread scheduler for dynamic multithreading on throughput processors
inferred← citeshttps://doi.org/10.1142/s0218126615501145openalex-snapshot
Simultaneous Multithreaded Matrix Processor
inferred← citeshttps://doi.org/10.1145/1815961.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferred← citeshttps://doi.org/10.1145/1816038.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferred← citeshttps://doi.org/10.1145/2000064.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferred← citeshttps://doi.org/10.1145/2024723.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferred← citeshttps://doi.org/10.1145/2366231.2337166openalex-snapshot
Simultaneous branch and warp interweaving for sustained GPU performance
inferred← citeshttps://doi.org/10.1145/2485922.2485954openalex-snapshot
SIMD divergence optimization through intra-warp compaction
inferred← citeshttps://doi.org/10.1145/2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferred← citeshttps://doi.org/10.1145/2508148.2485954openalex-snapshot
SIMD divergence optimization through intra-warp compaction
inferred← citeshttps://doi.org/10.1145/2847253openalex-snapshot
Iteration Interleaving--Based SIMD Lane Partition
inferred← citeshttps://doi.org/10.1145/3123939.3136952openalex-snapshot
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs
inferred← citeshttps://doi.org/10.1145/3352460.3358276openalex-snapshot
Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms
inferred← citeshttps://doi.org/10.1145/3422667openalex-snapshot
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
inferred← citeshttps://doi.org/10.1145/3582016.3582046openalex-snapshot
Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores
inferred← citeshttps://doi.org/10.17760/d20002060openalex-snapshot
The unified floating point vector coprocessor for reconfigurable hardware
inferred← citeshttps://doi.org/10.2200/s00647ed1v01y201505cac032openalex-snapshot
Single-Instruction Multiple-Data Execution
inferred← citeshttps://doi.org/10.48550/arxiv.1905.06238openalex-snapshot
Exploiting Fine-Grain Ordered Parallelism in Dense Matrix Algorithms
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