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A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
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Outgoing claims: the papers this work cites, builds on, or argues with.
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ParVec: vectorizing the PARSEC benchmark suite
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Scalability analysis of AVX-512 extensions
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Paving the way for China exascale computing
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Computer architecture: a quantitative approach
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UNIVERSITY OF CALIFORNIA
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Decoupled vector architectures
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Proceedings 2004 International Conference on Parallel Processing ICPP 2004
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Rodinia: A benchmark suite for heterogeneous computing
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Proceedings International Parallel and Distributed Processing Symposium
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So many states, so little time: verifying memory coherence in the Cray X1
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Proceedings of 21 International Symposium on Computer Architecture
inferredcites →https://doi.org/10.1109/isca45697.2020.00016openalex-snapshot
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
inferredcites →https://doi.org/10.1109/proc.1966.5273openalex-snapshot
Very high-speed computing systems
inferredcites →https://doi.org/10.1109/tvlsi.2019.2950087openalex-snapshot
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
inferredcites →https://doi.org/10.1145/1188455.1188677openalex-snapshot
S12---The HPC Challenge (HPCC) benchmark suite
inferredcites →https://doi.org/10.1145/1242531openalex-snapshot
Proceedings of the 4th international conference on Computing frontiers
inferredcites →https://doi.org/10.1145/1362622openalex-snapshot
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
inferredcites →https://doi.org/10.1145/2000064.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferredcites →https://doi.org/10.1145/2304576openalex-snapshot
Proceedings of the 26th ACM international conference on Supercomputing
inferredcites →https://doi.org/10.1145/2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferredcites →https://doi.org/10.1145/2518037.2491464openalex-snapshot
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
inferredcites →https://doi.org/10.1145/859618.859664openalex-snapshot
Overcoming the limitations of conventional vector processors
inferredcites →https://doi.org/10.1145/859662.859664openalex-snapshot
Overcoming the limitations of conventional vector processors
inferredcites →https://doi.org/10.21236/ada439315openalex-snapshot
Introduction to the HPCChallenge Benchmark Suite
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Test-Driving RISC-V Vector Hardware for HPC
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Challenges and Opportunities for RISC-V Architectures Towards Genomics-Based Workloads
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A New Cross-Product Instruction for RISC-V CPUs
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Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
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Vectorized FlashAttention with low-cost exponential computation in RISC-V vector processors
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Bicameral+ Cache: re-assessing split vector and scalar cache designs for increased efficiency
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A General Framework for Accelerator Management Based on ISA Extension
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Gem5-AVX: Extension of the Gem5 Simulator to Support AVX Instruction Sets
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CIA: Composable Instruction-Based Accelerators
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Shared Load-Store Unit for Instruction-Based Accelerators
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TapeFlow: Streaming Gradient Tapes in Automatic Differentiation
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PRAVE: Partial Out-of-Order Execution for Superscalar Processors with Vector Extension
inferred← citeshttps://doi.org/10.1109/dcis58620.2023.10335997openalex-snapshot
RISC-V for Genome Data Analysis: Opportunities and Challenges
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00063openalex-snapshot
Adaptable Register File Organization for Vector Processors
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071074openalex-snapshot
EVE: Ephemeral Vector Engines
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00061openalex-snapshot
VSA: A Hybrid Vector-Systolic Architecture
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ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Access
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00092openalex-snapshot
RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V
inferred← citeshttps://doi.org/10.1109/iiswc59245.2023.00036openalex-snapshot
Vector-Processing for Mobile Devices: Benchmark and Analysis
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00023openalex-snapshot
vACE: Exploring the Design Space of Vector Processing Units for Soft Error Vulnerability
inferred← citeshttps://doi.org/10.1109/ipdps54959.2023.00024openalex-snapshot
Accelerating CNN inference on long vector architectures via co-design
inferred← citeshttps://doi.org/10.1109/jssc.2026.3676416openalex-snapshot
Cygnus: A Heterogeneous Octa-Core RISC-V Vector Processor for Digital Signal Processing Applications
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Accelerating Vector Permutation Instruction Execution via Controllable Bitonic Network
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Python-Based Lightweight and Extensible RISC-V Simulator: Design and Implementation
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big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
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Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V
inferred← citeshttps://doi.org/10.1109/pdp66500.2025.00026openalex-snapshot
A Performance Analysis of Autovectorization on RVV RISC-V Boards
inferred← citeshttps://doi.org/10.1109/sbac-pad55451.2022.00031openalex-snapshot
Prof5: A RISC-V profiler tool
inferred← citeshttps://doi.org/10.1109/sbac-pad59825.2023.00013openalex-snapshot
Exploiting the Potential of Flexible Processing Units
inferred← citeshttps://doi.org/10.1109/socc66126.2025.11235386openalex-snapshot
Exploring RISC-V Instruction-Level Optimization Through Macro-Operation Fusion for TensorFlow-based Models
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Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor
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Precise Event Sampling on AMD Versus Intel: Quantitative and Qualitative Comparison
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BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge
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Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications
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Java Vector API: Benchmarking and Performance Analysis
inferred← citeshttps://doi.org/10.1145/3603781.3603942openalex-snapshot
RISC-V ISA Extension Toolchain Supports: A Survey
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Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V
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Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors
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Exploiting Vector Code Semantics for Efficient Data Cache Prefetching
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ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension
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Constructing a Supplementary Benchmark Suite to Represent Android Applications with User Interactions by using Performance Counters
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AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
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Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
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Rapid RISC-V Floating Point Vector Simulation
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Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors
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The RISC-V VecR extension: Adding internal registers to RVV
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An analysis of memory access patterns in RISC-V vector workloads on heterogeneous memory architectures
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MXM-RVV: Multicore and Multithreaded RISC-V Vectors
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RVV-Morpher: A Semantic-Aware Static Binary Rewriter for Cross-Version Portability in RVV
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Xtream: A Production-Level VM Cross-Cloud Disk Migration System with Stripe-Oriented Prefetching
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AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
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Desenvolvendo Ferramentas para Ensino de RISC-V com Python, Verilog, Matplotlib, SVG e ChatGPT
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