On the public citation graph
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
0 signed · 62 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0167-8191(85)90022-5openalex-snapshot
FACOM VP-100/200: Supercomputers with ease of use
inferredcites →https://doi.org/10.1109/2.485896openalex-snapshot
Spert-II: a vector microprocessor system
inferredcites →https://doi.org/10.1109/2.612252openalex-snapshot
Scalable processors in the billion-transistor era: IRAM
inferredcites →https://doi.org/10.1109/40.526924openalex-snapshot
MMX technology extension to the Intel architecture
inferredcites →https://doi.org/10.1109/40.848475openalex-snapshot
AltiVec extension to PowerPC accelerates media processing
inferredcites →https://doi.org/10.1109/40.865866openalex-snapshot
Implementing streaming SIMD extensions on the Pentium III processor
inferredcites →https://doi.org/10.1109/hpca.1996.501193openalex-snapshot
Decoupled vector architectures
inferredcites →https://doi.org/10.1109/isscc.2007.373611openalex-snapshot
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
inferredcites →https://doi.org/10.1109/mc.2005.239openalex-snapshot
Parallelism and the ARM instruction set architecture
inferredcites →https://doi.org/10.1109/micro.2004.9openalex-snapshot
Cache Refill/Access Decoupling for Vector Machines
inferredcites →https://doi.org/10.1109/micro.2008.4771788openalex-snapshot
Tradeoffs in designing accelerator architectures for visual computing
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/mm.2006.41openalex-snapshot
Synergistic Processing in Cell's Multicore Architecture
inferredcites →https://doi.org/10.1109/mm.2008.31openalex-snapshot
NVIDIA Tesla: A Unified Graphics and Computing Architecture
inferredcites →https://doi.org/10.1109/pact.2009.16openalex-snapshot
A Task-Centric Memory Model for Scalable Accelerator Architectures
inferredcites →https://doi.org/10.1109/proc.1966.5273openalex-snapshot
Very high-speed computing systems
inferredcites →https://doi.org/10.1145/1028176.1006736openalex-snapshot
The Vector-Thread Architecture
inferredcites →https://doi.org/10.1145/125826.126164openalex-snapshot
Radix sort for vector multiprocessors
inferredcites →https://doi.org/10.1145/1356058.1356085openalex-snapshot
Compiling for vector-thread architectures
inferredcites →https://doi.org/10.1145/1365490.1365500openalex-snapshot
Scalable Parallel Programming with CUDA
inferredcites →https://doi.org/10.1145/1367045.1367050openalex-snapshot
Implementing the scale vector-thread processor
inferredcites →https://doi.org/10.1145/1455567.1455593openalex-snapshot
A functional description of the Lincoln TX-2 computer
inferredcites →https://doi.org/10.1145/1654059.1654088openalex-snapshot
Performance evaluation of NEC SX-9 using real science and engineering applications
inferredcites →https://doi.org/10.1145/197405.197406openalex-snapshot
Compiler transformations for high-performance computing
inferredcites →https://doi.org/10.1145/2000064.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferredcites →https://doi.org/10.1145/339647.339693openalex-snapshot
Vector instruction set support for conditional operations
inferredcites →https://doi.org/10.1147/sj.251.0051openalex-snapshot
The IBM System/370 vector architecture
inferredcites →https://doi.org/10.5555/956417.956548openalex-snapshot
Universal mechanisms for data-parallel architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11265-016-1215-5openalex-snapshot
Memory Controller for Vector Processor
inferred← citeshttps://doi.org/10.1016/j.mejo.2015.03.012openalex-snapshot
Merging VLIW and vector processing techniques for a simple, high-performance processor architecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.04.007openalex-snapshot
Modular vector processor architecture targeting at data-level parallelism
inferred← citeshttps://doi.org/10.1109/asap.2014.6868668openalex-snapshot
PVMC: Programmable Vector Memory Controller
inferred← citeshttps://doi.org/10.1109/esscirc.2014.6942056openalex-snapshot
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
inferred← citeshttps://doi.org/10.1109/globalsip.2015.7418271openalex-snapshot
Programmable data parallel accelerator for mobile computer vision
inferred← citeshttps://doi.org/10.1109/jssc.2016.2519386openalex-snapshot
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI
inferred← citeshttps://doi.org/10.1109/l-ca.2011.34openalex-snapshot
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
inferred← citeshttps://doi.org/10.1109/micro.2014.48openalex-snapshot
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
inferred← citeshttps://doi.org/10.1109/tetc.2016.2554318openalex-snapshot
Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators
inferred← citeshttps://doi.org/10.1145/2749469.2750410openalex-snapshot
A variable warp size architecture
inferred← citeshttps://doi.org/10.1145/2898364openalex-snapshot
Vector Coprocessor Virtualization for Simultaneous Multithreading
inferred← citeshttps://doi.org/10.1145/3422667openalex-snapshot
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
inferred← citeshttps://doi.org/10.1145/3582016.3582046openalex-snapshot
Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores
inferred← citeshttps://doi.org/10.1145/3594543openalex-snapshot
Derrick: A Three-layer Balancer for Self-managed Continuous Scalability
inferred← citeshttps://doi.org/10.1145/3631528openalex-snapshot
Extension VM: Interleaved Data Layout in Vector Memory
inferred← citeshttps://doi.org/10.1145/3695880openalex-snapshot
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication
inferred← citeshttps://doi.org/10.1145/3716873openalex-snapshot
VersaTile: Flexible Tiled Architectures via Associative Processors
inferred← citeshttps://doi.org/10.19153/cleiej.19.1.1openalex-snapshot
Impact of Thresholds and Load Patterns when Executing HPC Applications with Cloud Elasticity
inferred← citeshttps://doi.org/10.5821/dissertation-2117-106493openalex-snapshot
On the design of power- and energy-efficient functional units for vector processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-351088openalex-snapshot
Novel techniques to improve the performance and the energy of vector architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95566openalex-snapshot
A novel access pattern-based multi-core memory architecture
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96236openalex-snapshot
Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-98086openalex-snapshot
Novel vector architectures for data management
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.