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Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/b105828openalex-snapshot
Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation
inferredcites →https://doi.org/10.1016/j.jpdc.2008.05.014openalex-snapshot
A performance study of general-purpose applications on graphics processors using CUDA
inferredcites →https://doi.org/10.1103/physrevc.66.044310openalex-snapshot
Quantum Monte Carlo calculations of A = 9 , 10 nuclei
inferredcites →https://doi.org/10.1103/physrevlett.74.4396openalex-snapshot
Quantum Monte Carlo Calculations of A ≤ 6 Nuclei
inferredcites →https://doi.org/10.1109/cgo.2011.5764683openalex-snapshot
Vapor SIMD: Auto-vectorize once, run everywhere
inferredcites →https://doi.org/10.1109/dsn.2003.1209939openalex-snapshot
ICR: in-cache replication for enhancing data cache reliability
inferredcites →https://doi.org/10.1109/hpca.2002.995703openalex-snapshot
A new memory monitoring scheme for memory-aware scheduling and partitioning
inferredcites →https://doi.org/10.1109/hpca.2002.995706openalex-snapshot
Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay
inferredcites →https://doi.org/10.1109/hpca.2007.346199openalex-snapshot
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
inferredcites →https://doi.org/10.1109/iccd.2009.5413143openalex-snapshot
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
inferredcites →https://doi.org/10.1109/iiswc.2006.302743openalex-snapshot
MineBench: A Benchmark Suite for Data Mining Workloads
inferredcites →https://doi.org/10.1109/ipdps.2010.5470465openalex-snapshot
Exploiting inter-thread temporal locality for chip multithreading
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2002.1003572openalex-snapshot
Drowsy caches: simple techniques for reducing leakage power
inferredcites →https://doi.org/10.1109/isca.2008.22openalex-snapshot
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2007.12openalex-snapshot
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot
The M5 Simulator: Modeling Networked Systems
inferredcites →https://doi.org/10.1109/mm.2009.9openalex-snapshot
Larrabee: A Many-Core x86 Architecture for Visual Computing
inferredcites →https://doi.org/10.1145/1128022.1128023openalex-snapshot
Chip multiprocessing and the cell broadband engine
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1454115.1454144openalex-snapshot
Leveraging on-chip networks for data cache migration in chip multiprocessors
inferredcites →https://doi.org/10.1145/1654059.1654082openalex-snapshot
Increasing memory miss tolerance for SIMD cores
inferredcites →https://doi.org/10.1145/1815961.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferredcites →https://doi.org/10.1145/356989.357011openalex-snapshot
Symbiotic jobscheduling for a simultaneous mutlithreading processor
inferredcites →https://doi.org/10.1145/378993.379244openalex-snapshot
Symbiotic jobscheduling for a simultaneous multithreaded processor
inferredcites →https://doi.org/10.21236/ada419598openalex-snapshot
Smart Memories: A Modular Reconfigurable Architecture
inferredcites →https://doi.org/10.7551/mitpress/9486.003.0016openalex-snapshot
Intel Threading Building Blocks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10617-020-09238-2openalex-snapshot
Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors
inferred← citeshttps://doi.org/10.1007/s11265-014-0944-6openalex-snapshot
Exploiting Tightly-Coupled Cores
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.12.001openalex-snapshot
SIMD stealing: Architectural support for efficient data parallel execution on multicores
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.03.010openalex-snapshot
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT
inferred← citeshttps://doi.org/10.1049/cje.2018.05.003openalex-snapshot
Memory Request Priority Based Warp Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00090openalex-snapshot
GPU Subwarp Interleaving
inferred← citeshttps://doi.org/10.1109/iiswc.2013.6704684openalex-snapshot
Pannotia: Understanding irregular GPGPU graph applications
inferred← citeshttps://doi.org/10.1109/mwscas.2019.8885180openalex-snapshot
Neuromorphic In-Memory Computing Framework using Memtransistor Cross-bar based Support Vector Machines
inferred← citeshttps://doi.org/10.1109/tce.2015.7389807openalex-snapshot
Programmable multimedia platform based on reconfigurable processor for 8K UHD TV
inferred← citeshttps://doi.org/10.1109/vldi-dat.2013.6533822openalex-snapshot
A distributed thread scheduler for dynamic multithreading on throughput processors
inferred← citeshttps://doi.org/10.1117/12.3011967openalex-snapshot
Chaotic multi-group optimization algorithm based on heterogeneous computing
inferred← citeshttps://doi.org/10.1145/2742060.2742112openalex-snapshot
Yield-aware Performance-Cost Characterization for Multi-Core SIMT
inferred← citeshttps://doi.org/10.1145/2749469.2750410openalex-snapshot
A variable warp size architecture
inferred← citeshttps://doi.org/10.1145/2872887.2750410openalex-snapshot
A variable warp size architecture
inferred← citeshttps://doi.org/10.1145/3582016.3582046openalex-snapshot
Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores
inferred← citeshttps://doi.org/10.14288/1.0166749openalex-snapshot
Locality and scheduling in the massively multithreaded era
inferred← citeshttps://doi.org/10.18130/v32z43openalex-snapshot
Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability
inferred← citeshttps://doi.org/10.3384/diss.diva-130723openalex-snapshot
Design of Energy-Efficient High-Performance ASIP-DSP Platforms
inferred← citeshttps://doi.org/10.48550/arxiv.1208.2374openalex-snapshot
Dynamic Warp Resizing in High-Performance SIMT
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